ADC12DL040CIVSSLASHNOPB datasheet(10/37 Pages) TI1

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AGND

To Internal Circuitry

I/O

ADC12DL040

SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013

www.ti.com

AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR =

+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,

parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C

(1) (2) (3) (4)

Typical

Limits

Units

Symbol

Parameter

Conditions

(5)

(Limits)

fCLK1

Maximum Clock Frequency

MHz (min)

fCLK2

Minimum Clock Frequency

MHz

tCH

Clock High Time

Duty Cycle Stabilizer On

12.5

ns (min)

tCL

Clock Low Time

Duty Cycle Stabilizer On

12.5

ns (min)

tr, tf

Clock Rise and Fall Times

Duty Cycle Stabilizer On

ns (max)

tCH

Clock High Time

Duty Cycle Stabilizer Off

12.5

ns (min)

tCL

Clock Low Time

Duty Cycle Stabilizer Off

12.5

ns (min)

tr, tf

Clock Rise and Fall Times

Duty Cycle Stabilizer Off

ns (max)

tCONV

Conversion Latency

Parallel mode

Clock Cycles

3.5

ns (min)

Data Output Delay after Rising Clock

tOD

Parallel mode

6.0

Edge

9.6

ns (max)

tCONV

Conversion Latency

Multiplex mode, Channel A

7.5

Clock Cycles

tCONV

Conversion Latency

Multiplex mode, Channel B

Clock Cycles

3.5

ns (min)

tOD

Data Output Delay after Clock Edge

Multiplex mode

6.0

ns (max)

tSKEW

ABb to Data Skew

±0.5

ns (max)

tAD

Aperture Delay

tAJ

Aperture Jitter

1.2

ps rms

tDIS

Data outputs into Hi-Z Mode

tEN

Data Outputs Active after Hi-Z Mode

1.0 µF on pins 4, 14; 0.1 µF on pins

tPD

Power Down Mode Exit Cycle

5,6,12,13; 10 µF between pins 5, 6 and

µs

between pins 12, 13

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate

conversions.

(2)

To specify accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.

(4)

Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.

(5)

Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing

Quality Level).

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