ADS5400HFSSLASHEM datasheet(35/47 Pages) TI1

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=(j

)

TOTAL

ADC

CLOCK

1/2

SNR(dBc)=-20xLOG10(2x

)

TOTAL

Clock Common Mode − V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G016

fS = 1 GSPS

fIN = 1498.5 MHz

fIN = 601.13 MHz

fIN = 100.33 MHz

fIN = 901.13 MHz

Clock Common Mode − V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G017

fS = 1 GSPS

fIN = 1498.5 MHz

fIN = 901.13 MHz

fIN = 100.33 MHz

fIN = 601.13 MHz

ADS5400-SP

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SLAS669D – SEPTEMBER 2010 – REVISED JANUARY 2014

Figure 35. ADS5400 SFDR vs Clock Common Mode

Figure 36. ADS5400 SNR vs Clock Common Mode

To understand how to determine the required clock jitter, an example is useful. The ADS5400 is capable of

achieving 58.7 dBFS SNR at 850 MHz of analog input frequency. To achieve SNR at 850 MHz, the external

clock source rms jitter must be at least 210fs when combined with the 125fs of internal aperture jitter in order for

the total rms jitter to be 244fs. A summary of maximum recommended rms clock jitter as a function of analog

input frequency is provided in Table 17 (using 125fs of internal aperture jitter). The equations used to create the

table are also presented.

Table 17. Recommended RMS Clock Jitter

INPUT FREQUENCY

MEASURED SNR

TOTAL JITTER

MAXIMUM EXT CLOCK JITTER

(MHz)

(dBc)

(fs rms)

125

58.1

1585

1580

600

57.8

318

342

850

57.7

244

210

1200

56.6

196

151

1700

54.7

172

119

Equation 1 and Equation 2 are used to estimate the required clock source jitter.

(1)

(2)

where:

jTOTAL = the rms summation of the clock and ADC aperture jitter;

jADC = the ADC internal aperture jitter which is located in the data sheet;

jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and

fIN = the analog input frequency.

Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the

clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.

For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not

required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see

Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC

Devices. Recommended clock distribution chips (CDCs) are the TI CDC7005 and CDCM7005. Depending on the

jitter requirements, a band pass filter (BPF) is sometimes required between the CDC and the ADC. If the

insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the clock source amplitude is

too low to begin with, an inexpensive amplifier can be placed between the CDC and the BPF.

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