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AD1981A Datasheet(PDF) 20 Page - Analog Devices |
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AD1981A Datasheet(HTML) 20 Page - Analog Devices |
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20 / 24 page ![]() REV. 0 AD1981A –20– Table I. Jack Sense Mute Table – JSMT [2:0] REF JS1 JS0 JSMT2 JSMT1 JSMT0 H.P. LINE MONO NOTES HEADPHONE LINE OUT OUT OUT OUT 0 OUT (0) OUT (0) 0 0 0 ACTIVE ACTIVE ACTIVE JS0 and JS1 1 OUT (0) IN (1) 0 0 0 ACTIVE ACTIVE ACTIVE Ignored 2 IN (1) OUT (0) 0 0 0 ACTIVE ACTIVE ACTIVE 3 IN (1) IN (1) 0 0 0 ACTIVE ACTIVE ACTIVE 4 OUT (0) OUT (0) 0 0 1 FMUTE FMUTE ACTIVE JS0 no mute action, 5 OUT (0) IN (1) 0 0 1 FMUTE ACTIVE ACTIVE JS1 mutes Line_out 6 IN (1) OUT (0) 0 0 1 ACTIVE FMUTE ACTIVE 7 IN (1) IN (1) 0 0 1 ACTIVE FMUTE ACTIVE 8 OUT (0) OUT (0) 0 1 0 FMUTE FMUTE ACTIVE JS0 no mute action, 9 OUT (0) IN (1) 0 1 0 FMUTE ACTIVE ACTIVE JS1 mutes Mono and 10 IN (1) OUT (0) 0 1 0 ACTIVE FMUTE FMUTE Line_out 11 IN (1) IN (1) 0 1 0 ACTIVE FMUTE FMUTE 12 OUT (0) OUT (0) 0 1 1 ** ** ** ** RESERVED 13 OUT (0) IN (1) 0 1 1 ** ** ** 14 IN (1) OUT (0) 0 1 1 ** ** ** 15 IN (1) IN (1) 0 1 1 ** ** ** 16 OUT (0) OUT (0) 1 0 0 FMUTE FMUTE ACTIVE JS0 mutes Mono, 17 OUT (0) IN (1) 1 0 0 FMUTE ACTIVE FMUTE JS1 no mute action 18 IN (1) OUT (0) 1 0 0 ACTIVE FMUTE ACTIVE 19 IN (1) IN (1) 1 0 0 ACTIVE ACTIVE FMUTE 20 OUT (0) OUT (0) 1 0 1 FMUTE FMUTE ACTIVE JS0 mutes Mono, 21 OUT (0) IN (1) 1 0 1 FMUTE ACTIVE FMUTE JS1 mutes Line_out 22 IN (1) OUT (0) 1 0 1 ACTIVE FMUTE ACTIVE 23 IN (1) IN (1) 1 0 1 ACTIVE FMUTE FMUTE 24 OUT (0) OUT (0) 1 1 0 FMUTE FMUTE ACTIVE JS0 mutes Mono, 25 OUT (0) IN (1) 1 1 0 FMUTE ACTIVE FMUTE JS1 mutes Mono and 26 IN (1) OUT (0) 1 1 0 ACTIVE FMUTE FMUTE Line_out 27 IN (1) IN (1) 1 1 0 ACTIVE FMUTE FMUTE 28 OUT (0) OUT (0) 1 1 1 ** ** ** ** RESERVED 29 OUT (0) IN (1) 1 1 1 ** ** ** 30 IN (1) OUT (0) 1 1 1 ** ** ** 31 IN (1) IN (1) 1 1 1 ** ** ** FMUTE = Output is forced to mute independent of the respective volume register setting. ACTIVE = Output is not muted and its status is dependent on the respective volume register setting. OUT = Nothing plugged into the jack and, therefore, the JS status is low (via the load resistor pull-down). IN = Jack has plug inserted and therefore the JS status is high (via the CODEC JS internal pull-up). Serial Configuration (Index 74h) This register is not reset when the reset register (Register 00h) is written. SPLNK SPDIF LINK: This bit enables the SPDIF to link with the DAC for data requesting. 0 = SPDIF and DAC are not linked. 1 = SPDIF and DAC are linked and receive same data requests (reset default). SPDZ SPDIF DACZ: 0 = Repeat last sample out the SPDIF stream if FIFO underruns (reset default). 1 = Forces “midscale” sample out the SPDIF stream if FIFO underruns. SPAL SPDIF ADC Loop Around: 0 = SPDIF transmitter is connected to the AC-LINK stream (reset default). 1 = SPDIF transmitter is connected to the digital ADC stream, not the AC-LINK. INTS INTERRUPT MODE SELECT: This bits selects the JS interrupt implementation path. 0 = Bit 0 SLOT 12 (Modem Interrupt) 1 = Slot 6 Valid Bit (MIC ADC Interrupt) CHEN Chain Enable: This bit enables chaining of a slave CODEC SDATA_IN stream into the ID0 Pin (45). 0 = Disable Chaining (Reset Default) 1 = Enable Chaining into ID0 Pin Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 74h Serial Configuration SLOT16 REGM2 REGM1 REGM0 X X X CHEN X X X INTS X SPAL SPDZ SPLNK 7001h |
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