THS789

SLOS776A – SEPTEMBER 2012 – REVISED DECEMBER 2015

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7.4 Device Functional Modes

7.4.1 Serial-Results Interface

The TMU captures time-stamp results and sends them to external logic using an LVDS serial-results port. The

serial-results port consists of a clock signal (RCLK), four strobe signals (Rstrobex) and four data signals

(Rdatax). The Rstrobex signal indicates that a time-stamp data transfer is about to begin for the corresponding

channel.

Table 1 shows the results transfer format and time range.

Table 1. Result Transfer Format and Time Range

RESULT TRANSFER FORMAT

TIME RANGE

40 bits

–7.158 s to 7.158 s

7.4.2 Resister Map Descriptions for All Channels and Central Register

Table 2. Control and Status Register Descriptions for All Channels

Register

Bit

Name

Function

LogicState

Description

0

Channel is disabled

Enable or disable channel X by powering down the

0

En_ChX

channel. Time to enable a channel is 200

μs.

1

Channel is enabled

00h

0

Input is disabled

20h

Enables or disables the input of channel X. Events are

1

ChX_IP_EN

prevented from entering a channel.

40h

1

Input is enabled

60h

0

Positive edge

Defines the polarity of the event inputX for the upcoming

2

Pol_X

timestamp generation.

1

Negative edge

Table 3. Control and Status Register Descriptions for All Channels

Register

Bit

Name

Function

Logic State

Description

0

Reserved

Reserved

x

1

Unused

Unused

x

01h

2

Unused

Unused

x

21h

41h

3

Unused

Unused

x

61h

4

Unused

Unused

x

5

Reserved

Reserved

0

0

DLL locked

0

DLL_Lock_X

Indicates the DLL lock status for channel X.

1

DLL not locked

04h

2

Reserved

Reserved

x

24h

0

FIFO not full

Indicates that the FIFO is full. Timestamps arriving

44h

3

FIFO_Full_X

while FIFO is full are lost.

1

FIFO full

64h

0

FIFO not empty

4

FIFO_Empty_X

Indicates that the FIFO is empty.

1

FIFO empty

10

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