THS789

SLOS776A – SEPTEMBER 2012 – REVISED DECEMBER 2015

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7.5 Programming

7.5.1 Host Processor Bus Interface

The THS789 device includes a high-speed serial interface to a host processor. The host interface is used for

writing or reading registers that reside in the TMU chip. These registers allow configuration of the device

functions. All registers are capable of both read and write operations unless otherwise stated.

7.5.1.1 Serial Interface

The TMU serial interface operates at speeds of up to 50 MHz. Register addresses are 8 bits long. Data words

are 16 bits wide, enabling more-efficient interface transactions. The serial bus implementation uses three

LVCMOS signals: HCLK, Hstrobe, and Hdata. The HCLK and Hstrobe signals are inputs only, and the Hdata

signal is bidirectional. The HCLK signal is not required to run continuously. Thus, the host processor may disable

the clock by setting it to a low state after the completion of any required register accesses.

When data is transferred into the device, Hdata is configured as an input bus, and data is latched on a rising

edge of HCLK. When data is transferred out of the part, Hdata is configured as an output bus, and data is

updated on the falling edge of HCLK. Hstrobe is the control signal that identifies the beginning of a host bus

transaction. Hstrobe must remain low for the duration of the transaction, and must go high for at least two clock

cycles before another transaction can begin.

7.5.1.2 Read vs Write Cycle

The first Hdata bit latched by HCLK in a transaction identifies the transaction type.

First Hdata bit = 1 for read; data flows out of the chip.

First Hdata bit = 0 for write; data flows into the chip.

7.5.1.3 Parallel (Broadcast) Write

Parallel write is a means of allowing identical data to be transferred to more than one channel in one transaction.

The second Hdata bit of a transaction indicates whether a parallel write occurs.

Second Hdata bit = 0; data goes to the selected channel.

Second Hdata bit = 1; data goes to all four channels.

7.5.1.4 Address

After the R/W bit and the parallel write bit, the following 8 bits on the Hdata line contain the source address of the

data word for a read cycle or the destination address of the data word for a write cycle. Address bits are shifted

in MSB first, LSB last.

Third HCLK – Address Bit 7 (MSB)

Tenth HCLK – Address Bit 0 (LSB)

7.5.1.5 Data

The data stream is 16 bits long, and it is loaded or read back MSB first, LSB last. The timing for read and write

cycles is different, as the drivers on Hdata alternate between going into high-impedance and driving the line.

7.5.1.6 Reset

Reset is an external hardware signal that places all internal registers and control lines into their default states.

The THS789 device resets after a power-up sequence (POR). Hardware reset is an LVCMOS active-low signal

and is required to stay low for approximately 100 ns.

Reset places the TMU in a predetermined idle state at power on, and anytime the system software initializes the

system hardware. In the idle state, the TMU ignores state changes on the Event inputs and never creates

timestamps. The TMU is capable of switching within 250

μs from the idle state to a state that creates accurate

timestamps.

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