TMS320C6472ECTZ datasheet(119/269 Pages) TI1

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DD33

DD1

DD2

and other 1.8-V

supplies

DD18

(DDR2)

REFSSSTL

DD15

and other 1.5-V

supplies

(RGMII)

REFHSTL

1.2-V SERDES

supplies

DD33

All other

power supplies

TMS320C6472

www.ti.com

SPRS612G

– JUNE 2009 – REVISED JULY 2011

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS

models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing

Analysis application report (literature number SPRA839). If needed, external logic hardware such as

buffers may be used to compensate any timing differences.

7.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

7.3

Power Supplies

7.3.1

Power-Supply Sequencing

TI recommends the power-supply sequence options shown in Figure 7-4 and Figure 7-5. For Option 2,

after the DVDD33 supply is stable, the remaining power supplies can be powered up at the same time as

CVDD as long as their supply voltage never exceeds the CVDD voltage until CVDD is stable. Note that the

word stable means voltages that have reached a valid level as described in Section 6.2. Some TI

power-supply devices include an "auto-track" feature that can be used to ensure multiple supply outputs

ramp at the same time to prevent one being higher than another during startup. In all of these sequencing

requirements, the intent is to prevent a subsequent power supply voltage from exceeding a previous

power supply until the previous supply has reached a stable value.

Figure 7-4. Power-Supply Sequence (Option 1)

Figure 7-5. Power-Supply Sequence (Option 2)

C64x+ Peripheral Information and Electrical Specifications

119

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