TMS28F008AST datasheet(19/52 Pages) TI1

19 / 52 page

TMS28F008Axy,TMS28F800Axy

1048576 BY 8BIT/524288 BY 16BIT

AUTOSELECT BOOT BLOCK FLASH MEMORIES

SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

programming operations

There are two CSM commands for programming: program setup and alternate program setup

(see Table 1). After the desired command code is entered, the WSM takes over and correctly sequences the

device to complete the program operation. During this time, the CSM responds only to status reads until the

program operation has been completed, after which all commands to the CSM become valid again. Once a

program command has been issued, the WSM normally cannot be interrupted until the program algorithm is

completed (see Figure 3 and Figure 4).

Taking RP to VIL during programming aborts the program operation. During programming, VPP must remain in

the appropriate VPP voltage range as shown in the recommended operating conditions table. Different

combinations of RP, WP, and VPP pin voltage levels ensure that data in certain blocks are secured, and,

therefore, cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and compared

during a program operation. If 1s are programmed, the memory cell contents do not change and no error occurs.

A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)

during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.

When the WSM status bit (SB7) is set to a logic-high level, signifying the nonprogram operation is terminated,

all commands to the CSM become valid again.

erase operations

There are two erase operations that can be performed by the TMS28F008Axy and TMS28F800Axy devices:

block erase and erase suspend/erase resume. An erase operation must be used to initialize all bits in an array

block to 1s. After block-erase confirm is issued, the CSM responds only to status reads or erase-suspend

commands until the WSM completes its task.

D block erasure

Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is

accomplished only by blocks; data at single address locations within the array cannot be erased individually.

The block to be erased is selected by using any valid address within that block. Note that different

combinations of RP, WP and VPP pin voltage levels ensure that data in certain blocks are secure and,

therefore, cannot be erased (see Table 2 for a list of combinations). Block erasure is initiated by a command

sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see Figure 5). A

two-command erase sequence protects against accidental erasure of memory contents.

Erase-setup and erase-confirm commands are latched on the rising edge of CE or WE, whichever occurs

first. Block addresses are latched during the block-erase-confirm command on the rising edge of CE or WE

(see Figure 15 and Figure 16). When the block-erase-confirm command is complete, the WSM

automatically executes a sequence of events to complete the block erasure. During this sequence, the block

is programmed with logic 0s, data is verified, all bits in the block are erased, and finally, verification is

performed to ensure that all bits are erased correctly. Monitoring of the erase operation is possible through

the status register (see “read status register” in the subsection “read operations”).

D erase suspend/erase resume

During the execution of an erase operation, the erase-suspend command (B0h) can be entered to direct the

WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to

respond only to the read-array, read-status-register, and erase-resume commands. During the

erase-suspend operation, array data should be read from a block other than the one being erased. To

resume the erase operation, an erase-resume command (D0h) must be issued to cause the CSM to clear

the suspend state previously set (see Figure 5 and Figure 6).

TMS28F008AST Datasheet(PDF) 19 Page - Texas Instruments

TMS28F008AST Datasheet(HTML) 19 Page - Texas Instruments

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