TMS28F008Axy,TMS28F800Axy

1048576 BY 8BIT/524288 BY 16BIT

AUTOSELECT BOOT BLOCK FLASH MEMORIES

SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998

31

POST OFFICE BOX 1443

switching characteristics for TMS28F008ASy or ’AEy and TMS28F800ASy or ’AEy over

recommended ranges of supply voltage (commercial and extended temperature ranges)

read operations

PARAMETER

ALT.

’28F008ASy 70

’28F800ASy 70

’28F008AEy 70

’28F800AEy 70

’28F008ASy 80

’28F800ASy 80

’28F008AEy 80

’28F800AEy 80

UNIT

PARAMETER

ALT.

SYMBOL

3 V

5 V

3 V

5 V

UNIT

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

ta(A)

Access time, from A0 − A18

(see Note 14)

tAVQV

100

70

120

80

ns

ta(E)

Access time, from CE

tELQV

100

70

120

80

ns

ta(G)

Access time, from OE

tGLQV

65

35

65

40

ns

tc(R)

Cycle time, read

tAVAV

100

70

120

80

ns

td(E)

Delay time, CE low to

low-impedance output

tELQX

0

0

0

0

ns

td(G)

Delay time, OE low to

low-impedance output

tGLQX

0

0

0

0

ns

tdis(E)

Disable time, CE to

high-impedance output

tEHQZ

55

25

55

30

ns

tdis(G)

Disable time, OE to

high-impedance output

tGHQZ

45

25

45

30

ns

th(D)

Hold time, DQ valid from

A0 − A17, CE, or OE,

whichever occurs first

(see Note 14)

tAXQX

0

0

0

0

ns

tsu(EB)

Setup time, BYTE from CE

low

tELFL

tELFH

7

5

5

5

ns

td(RP)

Delay time, output from RP

high

tPHQV

800

450

800

450

ns

tdis(BL)

Disable time, BYTE low to

DQ8 − DQ15 in the

high-impedance state

tFLQZ

100

70

120

80

ns

ta(BH)

Access time, from BYTE

going high

tFHQV

100

70

120

80

ns

NOTE 14: For 28F800 (8-bit configuration) A−1, A−1 −A18 with A−1 as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB

address.