TMS28F008Axy,TMS28F800Axy

1048576 BY 8BIT/524288 BY 16BIT

AUTOSELECT BOOT BLOCK FLASH MEMORIES

SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998

34

POST OFFICE BOX 1443

power-up and reset switching characteristics for TMS28F008AVy or ’ALy and TMS28F800AVy or

’ALy over recommended ranges of supply voltage (commercial and extended temperature ranges)

(see Notes 10, 11, and 12)

PARAMETER

ALT.

SYMBOL

’28F008AVy100

’28F800AVy 100

’28F008ALy100

’28F800ALy100

’28F008AVy120

’28F800AVy 120

’28F008ALy120

’28F800ALy120

UNIT

PARAMETER

ALT.

SYMBOL

3.3-V VCC

RANGE

3.3-V VCC

RANGE

UNIT

MIN

MAX

MIN

MAX

tsu(VCC)

Setup time, RP low to VCC at 3 V MIN or 3.6 V MAX

(see Note 13)

tPL5V

tPL3V

0

0

ns

ta(DV)

Access time, address valid to data valid

tAVQV

100

120

ns

tsu(DV)

Setup time, RP high before data valid

tPHQV

800

800

ns

th(RP3)

Hold time, VCC at 3 V (MIN) to RP high

t3VPH

2

2

µs

NOTES: 10. Characterization data available

11. All ac current values are RMS unless otherwise noted.

12. E and G are switched low after power up.

13. The power supply can switch low concurrently with RP going low.

switching characteristics for TMS28F008AVy or ’ALy and TMS28F800AV or ’ALy over

recommended ranges of supply voltage (commercial and extended temperature ranges)

read operations

PARAMETER

ALT.

SYMBOL

’28F008AVy 100

’28F800AVy 100

’28F008ALy100

’28F800ALy100

’28F008AVy 120

’28F800AVy 120

’28F008ALy120

’28F800ALy120

UNIT

PARAMETER

SYMBOL

3 V

3 V

UNIT

MIN

MAX

MIN

MAX

ta(A)

Access time, from A0 − A18 (see Note 14)

tAVQV

100

120

ns

ta(E)

Access time, from CE

tELQV

100

120

ns

ta(G)

Access time, from OE

tGLQV

65

65

ns

tc(R)

Cycle time, read

tAVAV

100

120

ns

td(E)

Delay time, CE low to low-impedance output

tELQX

0

0

ns

td(G)

Delay time, OE low to low-impedance output

tGLQX

0

0

ns

tdis(E)

Disable time, CE to high-impedance output

tEHQZ

55

55

ns

tdis(G)

Disable time, OE to high-impedance output

tGHQZ

45

45

ns

th(D)

Hold time, DQ valid from A0 − A17, CE, or OE, whichever occurs

first (see Note 14)

tAXQX

0

0

ns

tsu(EB)

Setup time, BYTE from CE low

tELFL

tELFH

7

5

ns

td(RP)

Delay time, output from RP high

tPHQV

800

800

ns

tdis(BL)

Disable time, BYTE low to DQ8 − DQ15 in the high-impedance

state

tFLQZ

100

120

ns

ta(BH)

Access time, from BYTE going high

tFHQV

100

120

ns

NOTE 14: For 28F800 (8-bit configuration) A−1, A−1 −A18 with A−1 as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB

address.