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TMS570LS0232PZ Datasheet(PDF) 48 Page - Texas Instruments |
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TMS570LS0232PZ Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 109 page ![]() TMS570LS0232 SPNS242A – OCTOBER 2014 – REVISED JUNE 2015 www.ti.com 6.8.3 Master/Slave Access Privileges The table below lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device. Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed in the "MASTERS" column can access that slave module. Table 6-18. Master / Slave Access Matrix SLAVES ON MAIN SCR Peripheral Control Registers, All Flash Module Bus2 Non-CPU Accesses Peripheral MASTERS ACCESS MODE Interface: to Program Flash CRC Memories, And All OTP, ECC, EEPROM and CPU Data RAM System Module Bank Control Registers And Memories CPU READ User/Privilege Yes Yes Yes Yes CPU WRITE User/Privilege No Yes Yes Yes HTU Privilege No Yes Yes Yes 48 System Information and Electrical Specifications Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0232 |
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