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TMS570LS0232PZ Datasheet(PDF) 85 Page - Texas Instruments

Part # TMS570LS0232PZ
Description  16- and 32-Bit RISC Flash Microcontroller
PDF  109 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS570LS0232PZ Datasheet(HTML) 85 Page - Texas Instruments

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TMS570LS0232
www.ti.com
SPNS242A – OCTOBER 2014 – REVISED JUNE 2015
7.7.4
MibSPI/SPI Master Mode I/O Timing Specifications
Table 7-13. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
40
256tc(VCLK)
ns
Pulse duration, SPICLK high (clock polarity =
tw(SPCH)M
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
0)
2(5)
ns
Pulse duration, SPICLK low (clock polarity =
tw(SPCL)M
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
1)
Pulse duration, SPICLK low (clock polarity =
tw(SPCL)M
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
0)
3(5)
ns
Pulse duration, SPICLK high (clock polarity =
tw(SPCH)M
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
1)
Delay time, SPISIMO valid before SPICLK
td(SPCH-SIMO)M
0.5tc(SPC)M – 6
low (clock polarity = 0)
4(5)
ns
Delay time, SPISIMO valid before SPICLK
td(SPCL-SIMO)M
0.5tc(SPC)M – 6
high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK
tv(SPCL-SIMO)M
0.5tc(SPC)M – tf(SPC) – 4
low (clock polarity = 0)
5(5)
ns
Valid time, SPISIMO data valid after SPICLK
tv(SPCH-SIMO)M
0.5tc(SPC)M – tr(SPC) – 4
high (clock polarity = 1)
Setup time, SPISOMI before SPICLK low
tsu(SOMI-SPCL)M
tf(SPC) + 2.2
(clock polarity = 0)
6(5)
ns
Setup time, SPISOMI before SPICLK high
tsu(SOMI-SPCH)M
tr(SPC) + 2.2
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK
th(SPCL-SOMI)M
10
low (clock polarity = 0)
7(5)
ns
Hold time, SPISOMI data valid after SPICLK
th(SPCH-SOMI)M
10
high (clock polarity = 1)
C2TDELAY*tc(VCLK) + 2*tc(VCLK) -
(C2TDELAY+2) * tc(VCLK) - tf(SPICS) +
CSHOLD = 0
Setup time CS active until
tf(SPICS) + tr(SPC) – 7
tr(SPC) + 5.5
SPICLK high (clock
ns
C2TDELAY*tc(VCLK) + 3*tc(VCLK) -
(C2TDELAY+3) * tc(VCLK) - tf(SPICS) +
polarity = 0)
CSHOLD = 1
tf(SPICS) + tr(SPC) – 7
tr(SPC) + 5.5
8(6)
tC2TDELAY
C2TDELAY*tc(VCLK) + 2*tc(VCLK) -
(C2TDELAY+2) * tc(VCLK) - tf(SPICS) +
CSHOLD = 0
Setup time CS active until
tf(SPICS) + tf(SPC) – 7
tf(SPC) + 5.5
SPICLK low (clock polarity
ns
C2TDELAY*tc(VCLK) + 3*tc(VCLK) -
(C2TDELAY+3) * tc(VCLK) - tf(SPICS) +
= 1)
CSHOLD = 1
tf(SPICS) + tf(SPC) – 7
tf(SPC) + 5.5
Hold time SPICLK low until CS inactive
0.5*tc(SPC)M + T2CDELAY*tc(VCLK) +
0.5*tc(SPC)M + T2CDELAY*tc(VCLK) +
ns
(clock polarity = 0)
tc(VCLK) - tf(SPC) + tr(SPICS) - 7
tc(VCLK) - tf(SPC) + tr(SPICS) + 11
9(6)
tT2CDELAY
Hold time SPICLK high until CS inactive
0.5*tc(SPC)M + T2CDELAY*tc(VCLK) +
0.5*tc(SPC)M + T2CDELAY*tc(VCLK) +
ns
(clock polarity = 1)
tc(VCLK) - tr(SPC) + tr(SPICS) - 7
tc(VCLK) - tr(SPC) + tr(SPICS) + 11
(C2TDELAY+1) * tc(VCLK) - tf(SPICS) –
ns
10
tSPIENA
SPIENAn Sample point
(C2TDELAY+1)*tc(VCLK)
29
11
tSPIENAW
SPIENAn Sample point from write to buffer
(C2TDELAY+2)*tc(VCLK)
ns
(1)
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2)
tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3)
For rise and fall timings, see Table 5-6.
(4)
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6)
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
Copyright © 2014–2015, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
85
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