TNETV1002IDZHK datasheet(31/102 Pages) TI1

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DSP Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

Table 3--5. Relationship Between BNKCMP and Bank Size

BNKCMP

MSB TO COMPARE

BANK SIZE

Bit 15

Bit 14

Bit 13

Bit 12

MSBs TO COMPARE

(16-BIT WORDS)

None

64K

000

32K

15--14

16K

15--13

15--12

The external memory interface can be disabled when not used. This feature can be used to reduce the power

consumption of the 5471 DSP subsystem. Table 3--6 lists the states of the external interface pins, when the

interface is disabled (EXIO=1).

Table 3--6. State of Signals When External Bus Interface is Disabled (EXIO = 1)

SIGNAL

STATE

SIGNAL

STATE

DSP_A(19--0)

Previous State

DSP_MSTRB

High Level

DSP_D(15--0)

High Impedance

DSP_IOSTRB

High Level

DSP_PS

High Level

DSP_R/W

High Level

DSP_DS

High Level

KBGPIO12/DSP_MSC†

High Level

DSP_IS

High Level

KBGPIO11/DSP_IAQz‡

High Level

† Only applies when KBGPIO12 is enabled to output DSP_MSC.

‡ Only applies when KBGPIO11 is enabled to output DSP_IAQ

3.3.3 Processor Mode Status Register

The 5471 DSP subsystem processor mode status register (PMST) differs from the typical C54x design in that

the PMST CLKOUT bit has no effect on the CLKOUT port of the subsystem. This port is always clocking when

the DSP subsystem’s PLL is active.

TNETV1002IDZHK Datasheet(PDF) 31 Page - Texas Instruments

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