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TNETV1002IDZHK Datasheet(PDF) 82 Page - Texas Instruments

Part # TNETV1002IDZHK
Description  Fixed-Point Digital Signal Processor
PDF  102 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV1002IDZHK Datasheet(HTML) 82 Page - Texas Instruments

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Electrical Specifications
72
June 2001 -- Revised December 2002
SPRS180C
6.12 Synchronous DRAM Timings
Table 6--28 and Table 6--29 assume testing over recommended operating conditions (see Figure 6--23
through Figure 6--29).
Table 6--28. Synchronous DRAM Timing Requirements
NO.
MIN
MAX
UNIT
6
tsu(DV-SCLKH)
Setup time, read data valid before SDRAM_CLK high
4.5
ns
7
th(SCLKH-DV)
Hold time, read data valid after SDRAM_CLK high
2
ns
Table 6--29. Synchronous DRAM Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
1
td(SCLKH-CSV)
Delay time, SDRAM_CLK high to chip select valid
0.5
11
ns
2
td(SCLKH-DQMV)
Delay time, SDRAM_CLK high to byte enable valid
0.5
11
ns
3
td(SCLKH-DQMIV)
Delay time, SDRAM_CLK high to byte enable invalid
0.5
11
ns
4
td(SCLKH-AV)
Delay time, SDRAM_CLK high to address valid
0.5
11
ns
5
td(SCLKH-AIV)
Delay time, SDRAM_CLK high to address invalid
0.5
11
ns
8
td(SCLKH-CASV)
Delay time, SDRAM_CLK high to SDRAM_CAS valid
0.5
11
ns
9
td(SCLKH-DV)
Delay time, SDRAM_CLK high to data valid
0.5
11
ns
10
td(SCLKH-DIV)
Delay time, SDRAM_CLK high to data invalid
0.5
11
ns
11
td(SCLKH-WEV)
Delay time, SDRAM_CLK high to SDRAM_WE valid
0.5
11
ns
12
td(SCLKH-RASV)
Delay time, SDRAM_CLK high to, SDRAM_RAS valid
0.5
11
ns
SDRAM_CLK
CSn
SDRAM_DQM[3:0]
SDRAM_A[C:0]†
DATA[31:00]
SDRAM_A[10]†
SDRAM_RAS
SDRAM_CAS
SDRAM_WE
SDRAM_A[R:0]†
BE1
BE2
BE3
BE4
Bank
Column
D1
D2
D3
D4
8
7
6
5
5
5
3
2
8
4
4
4
1
READ
† The values for R and C depend on the particular size of the SRAMs used.
Figure 6--23. SDRAM Read Command (CAS Latency 3)



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