TNETV1002IDZHK datasheet(72/102 Pages) TI1

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Electrical Specifications

June 2001 -- Revised December 2002

SPRS180C

6.9

Instruction Acquisition (DSP_IAQ) and Interrupt Acknowledge (DSP_IACK)

Timings

Table 6--14 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6--13).

Table 6--14. DSP_IAQ and DSP_IACK Switching Characteristics

PARAMETER

MIN

MAX

UNIT

td(CLKL-IAQL)

Delay time, DSP_CLKOUT low to DSP_IAQ low

1.5

11.5

td(CLKL-IAQH)

Delay time, DSP_CLKOUT low to DSP_IAQ high

1.5

11.5

td(A)IAQ

Delay time, address valid to DSP_IAQ low

td(CLKL-IACKL)

Delay time, DSP_CLKOUT low to DSP_IACK low

1.5

11.5

td(CLKL-IACKH)

Delay time , DSP_CLKOUT low to DSP_IACK high

1.5

11.5

td(A)IACK

Delay time, address valid to DSP_IACK low

th(A)IAQ

Hold time, DSP_IAQ high after address invalid

-- 2

th(A)IACK

Hold time, DSP_IACK high after address invalid

-- 2

tw(IAQL)

Pulse duration, DSP_IAQ low

2H--3

tw(IACKL)

Pulse duration, DSP_IACK low

2H--3

DSP_MSTRB

DSP_IACK

DSP_IAQ

DSP_A[19:0]

DSP_CLKOUT

td(A)IACK

td(A)IAQ

tw(IACKL)

th(A)IACK

td(CLKL-IACKL)

tw(IAQL)

th(A)IAQ

td(CLKL-IAQL)

td(CLKL-IACKH)

td(CLKL-IAQH)

Figure 6--13. DSP_IAQ and DSP_IACK Timings

TNETV1002IDZHK Datasheet(PDF) 72 Page - Texas Instruments

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