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TNETV1002IDZHK Datasheet(PDF) 6 Page - Texas Instruments |
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TNETV1002IDZHK Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 102 page  Contents vi June 2001 -- Revised December 2002 SPRS180C Section Page 4.3 MCU Peripherals 33 ................................................................. 4.3.1 MCU Ethernet Interface Module 33 ........................................... 4.3.2 MCU Universal Asynchronous Receiver/Transmitter (UART) Interfaces 35 ......... 4.3.3 MCU Serial Peripheral Interface (SPI) 37 ...................................... 4.3.4 MCU General-Purpose I/O 37 ............................................... 4.3.5 MCU Inter-Integrated Circuit (I2C) Interface 39 ................................. 4.3.6 MCU Timers 39 ............................................................ 4.3.7 MCU Interrupt Handler 40 ................................................... 4.4 MCU Power-Down Modes 41 ......................................................... 4.5 MCU Peripheral Clock Management 42 ................................................. 4.6 Initialization 43 ...................................................................... 4.6.1 Initial MCU Code 43 ........................................................ 4.6.2 DSP Boot Mode 44 ......................................................... 4.6.3 Emulation Support 44 ....................................................... 5 Documentation Support 46 ................................................................. 6 Electrical Specifications 47 ................................................................ 6.1 Absolute Maximum Ratings 47 ........................................................ 6.2 Recommended Operating Conditions 47 ................................................ 6.3 Electrical Characteristics Over Recommended Operating Case Temperature (Unless Otherwise Noted) 48 .............................................. 6.4 Package Thermal Resistance Characteristics 49 ......................................... 6.5 Timing Parameter Symbology 49 ...................................................... 6.5.1 Divide-By-Two/Divide-By-Four Clock Option Timing 50 .......................... 6.5.2 Multiply-By-N Clock Option (PLL Enabled) Timing 51 ........................... 6.6 Memory and Parallel I/O Interface Timing 52 ............................................ 6.6.1 Memory Read 52 .......................................................... 6.6.2 Memory Write 54 .......................................................... 6.6.3 Parallel I/O Port Read Timing Requirements 56 ................................ 6.6.4 Parallel I/O Port Write Switching Characteristics 57 ............................. 6.7 Ready Timing for Externally Generated Wait-States 58 ................................... 6.8 Interrupt Timings 61 ................................................................. 6.9 Instruction Acquisition (DSP_IAQ) and Interrupt Acknowledge (DSP_IACK) Timings 62 ....... 6.10 External Flag (DSP_XF) and DSP_TOUT Timings 63 .................................... 6.11 Multichannel Buffered Serial Port (McBSP) Timings 64 ................................... 6.11.1 McBSP Receive and Transmit Timings 64 ..................................... 6.11.2 McBSP General-Purpose Timings 67 ......................................... 6.11.3 McBSP as SPI Master or Slave Timings 68 .................................... 6.12 Synchronous DRAM Timings 72 ....................................................... 6.13 I2C Bus Timings 76 .................................................................. 6.14 MII Timings 78 ...................................................................... 6.15 ARM Clock Timings 80 ............................................................... 6.16 SPI Clock Timings 84 ................................................................ 7 Mechanical Data 87 ........................................................................ |
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