TNETV1002IDZHK datasheet(54/102 Pages) TI1

54 / 102 page

MCU Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

4.6.2 DSP Boot Mode

When the DSP comes out of reset, it begins execution from 0xFF80. It can execute code either from external

memory or from internal memory, depending on the value of the DSP_MPNMC bit in the MCU’s

DSP_PLL_REG register. Once the appropriate mode is set, and, if necessary, code is downloaded via the

API module, the MCU may release the DSP subsystem from reset by clearing the DSP_RESET bit in the MCU

subsystem’s CLKM _CNTL _RST register.

For the case where DSP execution starts from internal memory, the MCU should download the appropriate

DSP code via the API interface (before releasing the DSP from reset). This is done by properly setting the

DSP_MPNMC and DSP_APIBN bits in the DSP_PLL_REG MCU memory-mapped register, and then

downloading the code via the API interface. The DSP_APIBN bit, when 0, causes the 2K-word block of DSP

data memory at 0x3800--0x3FFF to appear also in DSP program space beginning at 0xF800.

Table 4--6 shows the combinations of the DSP_PLL_REG register DSP_MPNMC and DSP_APIBN bits that

control where the DSP fetches code immediately following release of DSP reset.

Table 4--6. DSP Boot Memory

DSP_MPNMC

DSP_APIBN

DSP BOOT MEMORY AT DSP PROGRAM SPACE ADDRESS 0xFF80

Shadow of the API-accessible on-chip data-space RAM

On-chip program-only RAM which is not accessible to the API module

Shadow of the API-accessible on-chip Data-space RAM

External DSP memory

4.6.3 Emulation Support

The 5471 provides flexible emulation capabilities. It supports both TI’s emulation tools and tools developed

by third parties.

Since the emulation tools may understand both the C54x™ DSP core and the ARM7TDMIE core, or just the

C54x™ DSP core, just the ARM7TDMIE core, or just the ARM7TDMI core, multiple emulation modes are

required. To allow configuration of the internal JTAG chains used by the various emulators, the 5471 samples

the EMU1 and EMU0 pins at TRST rising edge. Based on the values of these pins, the internal scan chain

is configured for different emulation modes. These modes are summarized in Table 4--7.

Table 4--7. Emulation Mode Selection

Values at TRST Rising Edge

SCAN CHAIN ORDER

EMU0

EMU1

SCANCHAIN ORDER

Only the ARM7TDMIE core is in the chain. (This is also the mode for tools which only understand

the ARM7TDMI core.)

Only the C54x

™ DSP core is in the chain

Reserved

ARM7TDMIE core followed by C54x

™ DSP core followed by ASIC Logic test access port (TAP)

controller

TNETV1002IDZHK Datasheet(PDF) 54 Page - Texas Instruments

TNETV1002IDZHK Datasheet(HTML) 54 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL