TMS570LS3137 datasheet(89/173 Pages) TI1

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EMIF_CLK

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

BASIC SDRAM

WRITE OPERATION

EMIF_CS[0]

EMIF_DQM[1:0]

EMIF_nRAS

EMIF_nCAS

EMIF_nWE

TMS570LS3137

www.ti.com

SPNS162C – APRIL 2012 – REVISED APRIL 2015

Figure 6-16. Basic SDRAM Write Operation

Table 6-29. EMIF Synchronous Memory Timing Requirements

NO.

MIN

MAX

UNIT

Input setup time, read data valid on

tsu(EMIFDV-EM_CLKH)

EMIFDATA[15:0] before EMIF_CLK rising

Input hold time, read data valid on

th(CLKH-DIV)

1.5

EMIFDATA[15:0] after EMIF_CLK rising

Table 6-30. EMIF Synchronous Memory Switching Characteristics

NO.

PARAMETER

MIN

MAX

UNIT

tc(CLK)

Cycle time, EMIF clock EMIF_CLK

tw(CLK)

Pulse width, EMIF clock EMIF_CLK high or low

td(CLKH-CSV)

Delay time, EMIF_CLK rising to EMIFnCS[0] valid

Output hold time, EMIF_CLK rising to EMIFnCS[0]

toh(CLKH-CSIV)

invalid

Delay time, EMIF_CLK rising to EMIFnDQM[1:0]

td(CLKH-DQMV)

valid

Output hold time, EMIF_CLK rising to

toh(CLKH-DQMIV)

EMIFnDQM[1:0] invalid

Delay time, EMIF_CLK rising to EMIFADDR[21:0]

td(CLKH-AV)

and EMIFBA[1:0] valid

Output hold time, EMIF_CLK rising to

toh(CLKH-AIV)

EMIFADDR[21:0] and EMIFBA[1:0] invalid

Delay time, EMIF_CLK rising to EMIFDATA[15:0]

td(CLKH-DV)

valid

System Information and Electrical Specifications

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TMS570LS3137 Datasheet(PDF) 89 Page - Texas Instruments

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