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TMS570LS3137 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS570LS3137 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 173 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS570LS3137 SPNS162C – APRIL 2012 – REVISED APRIL 2015 TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview 1.1 Features 1 • High-Performance Automotive-Grade • Multiple Communication Interfaces Microcontroller for Safety-Critical Applications – 10/100 Mbps Ethernet MAC (EMAC) – Dual CPUs Running in Lockstep • IEEE 802.3 Compliant (3.3-V I/O Only) – ECC on Flash and RAM Interfaces • Supports MII, RMII, and MDIO – Built-In Self-Test (BIST) for CPU and On-chip – FlexRay Controller With Two Channels RAMs • 8KB of Message RAM With Parity Protection – Error Signaling Module With Error Pin • Dedicated Transfer Unit (FTU) – Voltage and Clock Monitoring – Three CAN Controllers (DCANs) • ARM® Cortex®-R4F 32-Bit RISC CPU • 64 Mailboxes, Each With Parity Protection – Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline • Compliant to CAN Protocol Version 2.0B – FPU With Single- and Double-Precision – Standard Serial Communication Interface (SCI) – 12-Region Memory Protection Unit (MPU) – Local Interconnect Network (LIN) Interface – Open Architecture With Third-Party Support Controller • Operating Conditions • Compliant to LIN Protocol Version 2.1 – System Clock up to 180 MHz • Can be Configured as a Second SCI – Core Supply Voltage (VCC): 1.2 V Nominal – Inter-Integrated Circuit (I2C) – I/O Supply Voltage (VCCIO): 3.3 V Nominal – Three Multibuffered Serial Peripheral Interfaces – ADC Supply Voltage (VCCAD): 3.0 to 5.25 V (MibSPIs) • Integrated Memory • 128 Words With Parity Protection Each – 3MB of Program Flash With ECC – Two Standard Serial Peripheral Interfaces (SPIs) – 256KB of RAM With ECC • Two Next Generation High-End Timer (N2HET) – 64KB of Flash With ECC for Emulated Modules EEPROM – N2HET1: 32 Programmable Channels • 16-Bit External Memory Interface – N2HET2: 18 Programmable Channels • Common Platform Architecture – 160-Word Instruction RAM Each With Parity – Consistent Memory Map Across Family Protection – Real-Time Interrupt (RTI) Timer OS Timer – Each N2HET Includes Hardware Angle – 96-Channel Vectored Interrupt Module (VIM) Generator – 2-Channel Cyclic Redundancy Checker (CRC) – Dedicated High-End Transfer Unit (HTU) With • Direct Memory Access (DMA) Controller MPU for Each N2HET – 16 Channels and 32 Control Packets • Two 12-Bit Multibuffered ADC Modules – Parity Protection for Control Packet RAM – ADC1: 24 Channels – DMA Accesses Protected by Dedicated MPU – ADC2: 16 Channels Shared With ADC1 • Frequency-Modulated Phase-Locked Loop – 64 Result Buffers With Parity Protection Each (FMPLL) With Built-In Slip Detector • General-Purpose Input/Output (GPIO) Pins • Separate Nonmodulating PLL for FlexRay™ Capable of Generating Interrupts • Trace and Calibration Capabilities – Sixteen Pins on the ZWT Package – Embedded Trace Macrocell (ETM-R4) – Four Pins on the PGE Package – Data Modification Module (DMM) • IEEE 1149.1 JTAG, Boundary Scan and ARM – RAM Trace Port (RTP) CoreSight™ Components – Parameter Overlay Module (POM) • JTAG Security Module • Packages – 144-Pin Quad Flatpack (PGE) [Green] – 337-Ball Grid Array (ZWT) [Green] 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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