CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 26 of 51
1 = Enable Timer interrupt every 1.024 ms ; 0 = Disable Timer Interrupt every 1.024 ms.
Bit 3 : USB Hub Interrupt Enable
1 = Enable Interrupt on a Hub status change; 0 = Disable interrupt due to hub status change. (Refer to section 14.6.)
Bit 4 : Reserved .
Bit 5 : GPIO Interrupt Enable
1 = Enable Interrupt on falling/rising edge on any GPIO; 0 = Disable Interrupt on falling/rising edge on any GPIO (Refer to
section 14.7, 9.1 and 9.2.).
Bit 6 : I2C Interrupt Enable
1 = Enable Interrupt on I2C related activity; 0 = Disable I2C related activity interrupt. (Refer to section 14.8.)
Bit 7 : Reserved.
Bit 0: EPA0 Interrupt Enable
1= Enable Interrupt on data activity through endpoint A0; 0= Disable Interrupt on data activity through endpoint A0
Bit 1: EPA1 Interrupt Enable
1= Enable Interrupt on data activity through endpoint A1; 0= Disable Interrupt on data activity through endpoint A1
Bit 2: EPA2 Interrupt Enable
1= Enable Interrupt on data activity through endpoint A2; 0= Disable Interrupt on data activity through endpoint A2.
Bit 3: EPB0 Interrupt Enable
1= Enable Interrupt on data activity through endpoint B0; 0= Disable Interrupt on data activity through endpoint B0
Bit 4: EPB1 Interrupt Enable
1= Enable Interrupt on data activity through endpoint B1; 0= Disable Interrupt on data activity through endpoint B1
Bit [7..5] : Reserved
During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared,
effectively, disabling all interrupts
The interrupt controller contains a separate flip-flop for each interrupt. See Figure 14-3 for the logic block diagram of the interrupt
controller. When an interrupt is generated, it is first registered as a pending interrupt. It stays pending until it is serviced or a reset
occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable
registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction.
When servicing an interrupt, the hardware does the following:
1. Disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the state of this bit can be read at Bit 2 of the
Processor Status and Control Register, Figure 13-1).
2. Clears the flip-flop of the current interrupt.
3. Generates an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt
Vector, see Section 14.1).
The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user
can reenable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited
only by the available stack space.
The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value
just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI
instruction is executed.
USB Endpoint Interrupt Enable
Address 0X21
Bit #
7
65
43
21
0
Bit Name
Reserved
Reserved
Reserved
EPB1
Interrupt
Enable
EPB0
Interrupt
Enable
EPA2
Interrupt
Enable
EPA1
Interrupt
Enable
EPA0
Interrupt
Enable
Read/Write
–
–
–
R/W
R/W
R/W
R/W
R/W
Reset
–
––
00
00
0
Figure 14-2. USB Endpoint Interrupt Enable Register
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