DS3134 datasheet(62/203 Pages) DALLAS

Part #	DS3134

Description	Chateau Channelized T1 And E1 And HDLC Controller

PDF	203 Pages

Scroll/Zoom	100%

Manufacturer	DALLAS [Dallas Semiconductor]

Direct Link	https://www.maximintegrated.com/en.html

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DS3134

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CP[n]RD where n = 0 to 15 for each Port

See the Register Map in Section 3

5432

CHD7

CHD6

CHD5

CHD4

CHD3

CHD2

CHD1

CHD0

CHD15

CHD14

CHD13

CHD12

CHD11

CHD10

CHD9

CHD8

Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.

Bits 0 to 15 / DS0 Channel Data (CHD0 to CHD15). The 16-bit data that is to either be written into or

read from the PORT RAM specified by the CP[n]RDIS register.

Port RAM Indirect Access Figure 5.3B

CP[n]RDIS

CP[n]RD

Port RAM (one each for all 16 Ports; n = 0 to 15)

C[n]DAT0

R[n]CFG0

T[n]CFG0

C[n]DAT1

R[n]CFG1

T[n]CFG1

C[n]DAT2

R[n]CFG2

T[n]CFG2

C[n]DAT3

R[n]CFG3

T[n]CFG3

C[n]DAT4

R[n]CFG4

T[n]CFG4

...

C[n]DAT126

R[n]CFG126

T[n]CFG126

C[n]DAT127

R[n]CFG127

T[n]CFG127

DS3134 Datasheet(PDF) 62 Page - Dallas Semiconductor

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