DS3134 datasheet(3/203 Pages) DALLAS

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DS3134

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REVISION HISTORY

Version 1 (1/30/98)

Original release.

Version 2 (4/4/98)

Assigned signals to leads (Section 2.1).

Added more information to Sections 1, 5, 7, and 10.

Removed the P3VEN signal pin (Section 2.1 and 2.5).

Added FIFO Priority Control bits to the MC register (Section 4.2).

Added Abort and Bit Stuffing Control bits to the RHCD and THCD registers (Section 6.2).

Changed the Absolute Maximum Voltage Rating and IOH numbers (Section 12).

Changed the Low Water Mark definition (Section 7.1).

Added Section 14 on Applications.

Version 3 (6/22/98)

1. Corrected JTRST* lead from V19 to U19 (Section 2.1).

2. Added TEST lead at C3 (Section 2.1).

3. Added the Valid Receive Done Queue Descriptor bit (Section 8.1.4).

4. Corrected JTAG Device Code from 0000614Ch to 00006143h (Section 11.3).

5. Changed the order of the TABTE & TZSD bits in the THCD Register (Section 6.2).

6. Added JTAG Scan Control Information into Table 11.4A (Section 11.4).

7. Added Minimum Grant & Maximum Latency Settings to PINTL0 (Section 9.2).

8. Remove the HDLC channel restriction that required channels 1 to 128 to be assigned to ports 0 to 7

and HDLC channels 129 to 256 to be assigned to port 8 to 15 (Sections 1, 5.1, 5.3 and 6.1).

Version 4 (11/18/98)

Added information about queues full and empty states (Sections 8.1.3, 8.1.4, 8.2.3, and 8.2.4).

Changed BERT ones and zeros detector from 32 consecutive to 31 consecutive (Section 5.6).

Changed BERT Bit and Error Counters to count during loss of receive synchronization (Section 5.6).

Corrected Table 1E (Section 1).

Added bit numbers to register descriptions.

Changed Local Bus Configuration Mode AC Timing Parameter A7 from 5ns to 40ns. (Section 12).

Version 5 (09/01/99)

1. Typos corrections and add clarifications.(Section 2.5, 3.5, 4.4, 5.3, 5.5, 5.6, 6.2, 7.1, 8.1.1, 8.2.3)

2. Change the number of T1/E1 support from 64 to 56 due to design over sight (Section 1)

3. Added clarifications for Receive High Water Mark and corrected Transmit Low Water Mark to a

value from 1 to smaller or equal to N –2, where N = the number of linked blocks.

4. Removed bit 1 of the RDMAQ register, this function is automatically implemented. Please refer to

section 8.1.3 (page 90)

5. Figure 10.3A signal LRD* is moved back one LCLK cycle to align with the rising edge of LCLK #1.

6. Figure 103B signal LWR* is moved back one LCLK cycle to align with the rising edge of LCLC #1.

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