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DS3134 Datasheet(PDF) 54 Page - Dallas Semiconductor

Part # DS3134
Description  Chateau Channelized T1 And E1 And HDLC Controller
PDF  203 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3134 Datasheet(HTML) 54 Page - Dallas Semiconductor

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DS3134
54 of 203
LAYER ONE BLOCK DIAGRAM Figure 5.1A
RS
RC
RD
SLOW
HDLC
(One
per
Port)
FAST
HDLC
Layer One
State Machine
Receive
Transmit
Channel-
ized
Local
Loop-
Back
(CLLB)
Channel-
ized
Network
Loop-
Back
(CNLB)
V.54
Detector
PORT
RAM
(see
Sec.
5.3)
Invert
Clock /
Data /
Sync
Local
Loop-
Back
(LLB)
Invert
Clock /
Data /
Sync
Force
All
Ones
TC
TD
TS
Over-
Sample
with
PCLK
Un-
Channel-
ized
Network
Loopback
(UNLB)
Over-
Sample
with
PCLK
BERT/
Fast
HDLC
Mux
BERT Mux
(see Figure 5.5A)
1 of 16
LLB
UNLB
Port
0 & 1
Only
To /
From
FIFO
Block
l1_bd
Ports 0 & 1 Only



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