NCV8853

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2

Figure 1. NCV8853 Application Diagram

Figure 2. NCV8853 Simple Block Diagram

PG

GDRV

ISNS

GND

VIN

VIN

VO

FB

COMP

EN/SYNC

8

GDRV

VIN

VREF

DRIVE

LOGIC

FAULT

LOGIC

CSA

ISNS

7

6

3

COMP

VEA

5

GND

PWM

SCP

OCP

UVLO

OSC

CLAMP

4

FB

2

EN/SYNC

SS

CL

1

PG

EN/SYNC

+

PG

PIN DESCRIPTIONS

No

Pin Symbol

Function

1

PG

Power good output. Use a pull−up resistor to 5.0 V. PG is pulled low when power is not good.

2

EN/SYNC

Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled

into sleep mode when this pin is brought low for longer than the enable time−out period.

3

COMP

Output of the voltage error amplifier. An external compensator network from COMP to GND is used to sta-

bilize the converter and tailor transient performance.

4

FB

Output voltage feedback. A resistor from the output voltage to FB with another resistor from FB to GND

creates a voltage divider for regulation and programming of the output voltage.

5

GND

Ground reference.

6

GDRV

Gate driver output. Connect to gate of the external P−channel MOSFET. A series resistance can be added

from GDRV to the gate to tailor EMC performance.

7

ISNS

Current sense input. Connect this pin to the source of the external P−channel MOSFET, through a current−

sense resistor to VIN to sense the switching current for regulation and current limiting.

8

VIN

Main power input for the IC.