 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LM12L458 Datasheet(PDF) 21 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
LM12L458 Datasheet(HTML) 21 Page - National Semiconductor (TI) |
|
|
21 / 36 page  2.0 Internal User-Programmable Registers (Continued) Bits 12–15 are used to store the user-programmable acqui- sition time. The Sequencer keeps the internal S/H in the ac- quisition mode for a fixed number of clock cycles (nine clock cycles, for 12-bit + sign conversions and two clock cycles for 8-bit + sign conversions or “watchdog” comparisons) plus a variable number of clock cycles equal to twice the value stored in Bits 12–15. Thus, the S/H’s acquisition time is (9 + 2D) clock cycles for 12-bit + sign conversions and (2 + 2D) clock cycles for 8-bit + sign conversions or “watchdog” com- parisons, where D is the value stored in Bits 12–15. The minimum acquisition time compensates for the typical inter- nal multiplexer series resistance of 2 k Ω, and any additional delay created by Bits 12–15 compensates for source resis- tances greater than 80 Ω. (For this acquisition time discus- sion, numbers in ( ) are shown for the LM12L458 operating at 6 MHz. The necessary acquisition time is determined by the source impedance at the multiplexer input. If the source resistance (R S) < 80Ω and the clock frequency is 6 MHz, the value stored in bits 12–15 (D) can be 0000. If R S > 80Ω, the following equations determine the value that should be stored in bits 12–15. D = 0.45 x R S xfCLK for 12-bits + sign D = 0.36 x R S xfCLK for 8-bits + sign and “watchdog” R S is in kΩ and fCLK is in MHz. Round the result to the next higher integer value. If D is greater than 15, it is advisable to lower the source impedance by using an analog buffer be- tween the signal source and the LM12L458’s multiplexer in- puts. Instruction RAM “01” The second Instruction RAM section is selected by placing a “01” in Bits 8 and 9 of the Configuration register. A4 A3 A2 A1 A0 Purpose Type D7 D6 D5 D4 D3 D2 D1 D0 000 Instruction RAM (RAM Pointer = 00) VIN− VIN+ 0 to 0 R/W Pause Loop 111 000 Watch- dog 0 to 1 R/W Acquisition Time 8/12 Timer Sync 111 000 Instruction RAM (RAM Pointer = 01) 0 to 0 R/W Comparison Limit #1 111 000 0 to 1 R/W Don’t Care >/< Sign 111 000 Instruction RAM (RAM Pointer = 10) 0 to 0 R/W Comparison Limit #2 111 000 0 to 1 R/W Don’t Care >/< Sign 111 1 0000 Configuration Register R/W I/O Auto Chan Stand- Full Auto- Reset Start Sel Zeroec Mask by Cal Zero 1 0001 R/W Don’t Care DIAG Test =0 RAM Pointer 1 0010 Interrupt Enable Register R/W INT7 Don’t Care INT5 INT4 INT3 INT2 INT1 INT0 1 0011 R/W Number of Conversions in Conversion Sequencer Address to FIFO to Generate INT2 Generate INT1 1 0100 Interrupt Status Register R INST7 “0” INST5 INST4 INST3 INST2 INST1 INST0 1 0101 R Actual Number of Conversions Results in Conversion FIFO Address of Sequencer Instruction being Executed 1 0110 Timer Register R/W Timer Preset: Low Byte 1 0111 R/W Timer Preset: High Byte 1 1000 Conversion FIFO R Conversion Data: LSBs 1 1001 R Address or Sign Sign Conversion Data: MSBs 1 1010 Limit Status Register R Limit #1 Status 1 1011 R Limit #2 Status FIGURE 14. LM12L458 Memory Map for 8-Bit Wide Databus (BW = “1” and Test Bit = “0”) www.national.com 21 |
Similar Part No. - LM12L458 |
|
Similar Description - LM12L458 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
