ZSC31010CEC datasheet(36/43 Pages) IDT

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ZSC31010 Datasheet

January 20, 2016

4.2.

Absolute Analog Voltage Output

The figure below shows an application circuit for an absolute voltage output configuration with temperature

compensation via internal temperature PTAT, and external JFET regulation for all industry standard applications.

The gate-source cutoff voltage (VGS) of th

e selected JFET must be ≤ -2 V.

Figure 4.2

Absolute Analog Voltage Output

ZSC31010

Bsink

VBP

N/C

VBN

VSS

SIG

VDD

Vgate

0.1

Vsupply

Ground

+5.5 to +30 V

OUT

Optional Bsink

MMBF4392

10 nF

The output signal range can be one of the following options:

• 0 to 1 V analog output. The absolute voltage output reference is trimmable: 1 V (± 3 mV) in the 1 V output

mode via a 4-bit EEPROM field (see section 2.4.3).

• Rail-to-rail analog output. The on-chip reference for the JFET regulator block is trimmable: 5 V (± 15 mV) in

the ratiometric output mode via a 4-bit EEPROM field (see section 2.4.3).

4.3.

Three-Wire Ratiometric Output with Over-Voltage Protection

The figure below shows an application circuit for a ratiometric output configuration with temperature compensation

via an internal diode. In this application, the JFET is used for over-voltage protection. JFET_Cfg bits [14:13] in

EEPROM are configured to 5.5 V. There is an additional maximum error of 8 mV caused by the non-zero rON of

the limiter JFET.

Figure 4.3

Ratiometric Output, Temperature Compensation via Internal Diode

ZSC31010

Bsink

VBP

N/C

VBN

VSS

SIG

VDD

Vgate

0.1

Vsupply

Ground

+4.5 to +5.5 V

OUT

Optional Bsink

J107 Vishay

10 nF

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