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ZSC31010CEC Datasheet(PDF) 7 Page - Integrated Device Technology |
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ZSC31010CEC Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 43 page ![]() ZSC31010 Datasheet © 2016 Integrated Device Technology, Inc. 7 January 20, 2016 1.3. Electrical Parameters See important table notes at the end of the table. Note: For parameters marked with an asterisk, there is no verification in mass production; the parameter is guaranteed by design and/or quality observation. Parameter Symbol Conditions Min Typ Max Unit 1.3.1. Supply/Regulation Characteristics Supply Voltage VDD 2.7 5.0 5.5 V Supply Current (varies with update rate and output mode) IDD At minimum update rate 0.25 mA At maximum update rate 1.0 1.2 Temperature Coefficient – Regulator (worst case) * TCREG Tem. -10°C to 120°C 35 ppm/K Temp. < -10°C and > 120°C 100 Power Supply Rejection Ratio * PSRR DC < 100 Hz (JFET regulation loop using mmbf4392 and 0.1 µF decoupling cap) 60 dB AC < 100 kHz (JFET regulation loop using mmbf4392 and 0.1 mF decoupling cap) 45 dB Power-On Reset Level POR 1.4 2.6 V 1.3.2. Analog Front-End (AFE) Characteristics Leakage Current Pin VBP,VBN IIN_LEAK ±10 nA 1.3.3. EEPROM Parameters Number Write Cycles nWRI_EEP At 150 °C At 85 °C 100 100k Cycles Data Retention tWRI_EEP At 100 °C 10 Years 1.3.4. A/D Converter Characteristics ADC Resolution rADC 14 Bit Integral Nonlinearity (INL) 1) INLADC -4 +4 LSB Differential Nonlinearity (DNL) * DNLADC -1 +1 LSB Response Time TRES,ADC Varies with update rate. Value given at fastest rate. 1 ms 1.3.5. Analog Output (DAC and Buffer) Characteristics Max. Output Current IOUT Max. current maintaining accuracy 2.2 mA Resolution rOUT Referenced to VDD 11 Bit Absolute Error EABS DAC input to output -10 +10 mV Differential Nonlinearity * DNL No missing codes -0.9 +1.5 LSB11Bit Upper Output Voltage Limit VOUT RL = 2.5 kΩ 95% VDD Lower Output Voltage Limit VOUT 16.5 mV |
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