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ZSC31010CEC Datasheet(PDF) 6 Page - Integrated Device Technology

Part # ZSC31010CEC
Description  Analog Output Sensor Signal Conditioner
PDF  43 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ZSC31010CEC Datasheet(HTML) 6 Page - Integrated Device Technology

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ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
6
January 20, 2016
1
Electrical Characteristics
1.1.
Absolute Maximum Ratings
Note: The absolute maximum ratings are stress ratings only. The device might not function or be operable above
the operating conditions given in section 1.2. Stresses exceeding the absolute maximum ratings might also
damage the device. In addition, extended exposure to stresses above the recommended operating conditions
might affect device reliability. IDT does not recommend designing to the “Absolute Maximum Ratings.”
Parameter
Symbol
Conditions
Min
Max
Unit
Analog Supply Voltage
VDD
-0.3
6.0
V
Voltages at Analog I/O – In Pin
VINA
-0.3
VDD+0.3
V
Voltages at Analog I/O – Out Pin
VOUTA
-0.3
VDD+0.3
V
Storage Temperature Range
TSTG
-50
150
°C
Storage Temperature Range
TSTG <10h
For periods < 10 hours
-50
170
°C
Note: Also see Table 6.1 regarding soldering temperature and storage conditions for the SOP-8 package.
1.2.
Recommended Operating Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Analog Supply Voltage to Ground
VDD
2.7
5.0
5.5
V
Analog Supply Voltage (with external
JFET Regulator)
VSUPP
5.5
7
30
V
Common Mode Voltage
VCM
1
VDDA - 1.3
V
Ambient Temperature Range
1, 2)
TAMB
-50
150
°C
External Capacitance between VDD and
Ground
CVDD
100
220
470
nF
Output Load Resistance to VDD
RL,OUT
2.5
10
k
Ω
Output Load Resistance to VSS
3) 4)
RL,OUT
2.5
20
k
Ω
Output Load Capacitance
5)
CL,OUT
1
10
15
nF
Bridge Resistance
6)
RBR
0.2
100
k
Ω
Power ON Rise Time
tPON
100
ms
1) Note that the maximum EEPROM programming temperature is 85°C.
2) If buying die, designers should use caution not to exceed maximum junction temperature by proper package selection.
3) When using the output for digital calibration, no pull down resistor is allowed.
4) For loads less than 20 k
Ω to VSS an equivalent strength (or lower) pull-up resistor must be added.
5) Using the output for digital calibration, C
L,OUT is limited by the maximum rise time TZAC,rise.
6) Note: Minimum bridge resistance is only a factor if using the Bsink feature. The nominal R
DS(ON) of the Bsink transistor is 10
Ω when
operating at VDD = 5 V, and 15
Ω when operating at V
DD = 3.0 V. This does give rise to a ratiometricity inaccuracy that becomes greater
with low bridge resistances.



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