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LMC1982 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LMC1982 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 14 page  Connection Diagrams Pin Description CLK (1) The INTERMETAL (IM) Bus clock is applied to the CLOCK pin. This input accepts a TTL or CMOS level signal. The input is used to clock the DATA signal. A data bit must be valid on the rising clock edge. DIGITAL INPUT 1 & 2 (2, 3) Internally tied high to V + through a 30 k Ω pull-up resistor, these inputs allow a periph- eral device to place any single-bit, active low digital information onto the IM Bus. It is then sent out to the controlling device through the DATA pin. Examples of such information could include indication of the presence of a Second Audio Program (SAP) or an FM ste- reo carrier. INPUTS1&2 (4, 25; 5, 24) These are the LMC1982’s two stereo input pairs. SELECT OUT (6, 23) The selected INPUT signal is available at this output. This feature allows external signal processors such as noise reduction or graphic equalizers to be used. This output can typically sink 1 mA. These pins should be capacitively coupled to pins 7 and 22, re- spectively, if no external processor is used. SELECT IN (7, 22) These are the inputs that an external signal processor uses to return a signal to the LMC1982. These pins should be capacitively coupled to pins 6 and 23, respectively, if no external processor is used. TONE IN (8, 21) These are the inputs to the tone control am- plifier. See the Application Information sec- tion titled “Tone Control Response”. TONE OUT (9, 20) Tone control amplifier output. See the Appli- cation Information section titled “Tone Control Response”. OP AMP OUT (10, 19) These outputs are used with external tone control capacitors. Internally, this output is applied to the volume attenuators. LOUDNESS (11, 18) The output signal on these pins is a voltage taken from the volume attenuator’s −40 dB tap point. An external R–C network is con- nected to these pins. ENHANCED STEREO (12, 17) An external R–C network is connected across these pins. This provides left-right channel cross-coupling and cancellation to create an enhanced stereo channel separa- tion effect. MAIN OUTPUT (13, 16) The output signal from these pins drives a stereo power amplifier. The output can typi- cally sink 1 mA. BYPASS (14) A 10 µF capacitor is connected between this pin and ground to provide an AC ground for the internal half-supply voltage reference. GROUND (15) This pin is connected to analog ground. V+ (26) This is the power supply connection. The LMC1982 is operational with supply voltages from 6V to 12V. This pin should be bypassed to ground through a 1.0 µF capacitor. ID (27) This is the IDENTITY digital input that, when low, signals the LMC1982 to receive, from a controlling device, a device address (40 H–47H), present on the DATA line. DATA (28) This is the serial data input for communica- tions sent by a controller. The controller must have open drain outputs used with external pull-up resistors. The data rate has a maxi- mum frequency of 1 MHz. The LMC1982 re- quires 16 bits of data to control or change a function: the first 8 bits select the LMC1982 and one of eight functions. The final eight bits set the function to a desired value. The data must be valid on the rising edge of the CLOCK input signal. DS011028-2 Top View Order Number LMC1982CIN See NS Package Number N28B DS011028-12 Top View Order Number LMC1982CIV See NS Package Number V28A www.national.com 6 |
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