are serially shifted from the controller to the LMC1982. This

is followed by 8 bits of function value data. Data present in

the internal shift register is latched and the instruction is

executed.

Application Information

INPUT SELECTOR

The LMC1982’s input selector and mode control are shown

in

Figure 2. The input selector selects one of two stereo sig-

nal sources or a mute function with typical attenuation of

100 dB. The selected signals are then sent to a mode control

matrix. As shown in

Table 1, the matrix provides normal ste-

reo or can direct either channel to both LEFT or RIGHT SE-

LECT OUTPUTs. The third matrix mode is normal stereo.

The control matrix output is buffered and appears on each

channel’s respective SELECT OUT pin (6, 23). Switching

noise is kept to a minimum when mute is selected by using

a50 k

Ω bias resistor.

Noise performance is optimized through the use of emitter

followers in the mode control matrix’s output. Internal 50 k

Ω

resistors are connected to each input selector pin to provide

the proper bias point for the emitter follower buffers. Each in-

ternal 50 k

Ω bias resistor is connected to a common

half-supply (V

and 23 (SELECT OUT) that is 1.4V below V

3.1V with V

put pins (4, 5, 24, and 25), input signal should be AC coupled

through a 1 µF capacitor.

The output signal at pins 6 and 23 can be used to drive ex-

teral audio processing circuits such as noise reduction

(LM1894–DNR or Dolby) or graphic equalizers (LMC835). It

is important that if any noise reduction is used it be placed

ahead of any tone controls or equalizers in the external cir-

cuit path to preserve the frequency spectrum of the selected

input signal. Otherwise, any frequency equalization could

prevent the proper operation of the noise reduction circuit. If

no external processor is used, a capacitor should be used to

couple the SELECT OUT signals directly to pins 7 and 22,

respetively.

MINIMUM LOAD IMPEDANCE

The LMC1982 employs emitter-followers to buffer the se-

lected stereo channels. The buffered signals are available at

pins 6 and 23 (SELECT OUT). The SELECT OUT buffers op-

erate with a typical bias current 1 mA.

The Electrical Specifications table lists a maximum input sig-

nal of 2.0 V

pins. This distortion level is achieved when the minimum AC

load impedance seen by the SELECT OUT pins is 2.5 k

Ω

(2.5V/1 mA). Using lower load impedances results in clipping

at lower output levels. If the load impedance is DC-coupled,

an increased quiescent current can flow. Latch-up may occur

DS011028-5

FIGURE 1. Typical Application

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