© VITESSE SEMICONDUCTOR CORPORATION

Page 3

8/28/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC6048

G52335-0, Rev. 4.0

High-Speed Octal

Programmable Timing Generator

Figure 1: Input Interleave

Figure 2: Functional Timing Diagram

Time Set Input (TSET<0:9>)

This is a 10-bit TTL bus that controls the delay value of the vernier. The 3 MSBs control the 800MHz shift

register and the 7 LSBs control the fine delay element. The TSET data is clocked in by a pulse generated from

the input data. The setup time of the TSET data is the same as the input signals (INA, INB). The TSET data

must be stable by the time the input edge arrives at the input pin and data must then be held stable for at least

3.5ns after the input edge arrives at the pin.

TSET_CLK

D

SET

CLR

Q

DQ

D

SET

CLR

Q

DQ

D

SET

PLL

CLR

400MHz

800MHz

Q

DQ

DATA

INxA

INxB

RCK

FSEL

BYP

TSET[0:9]

INA

INB

RCK

OUT

TSET (0000000000)

OUT

TSET (1111111111)