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ST25R3911B Datasheet(PDF) 37 Page - STMicroelectronics |
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ST25R3911B Datasheet(HTML) 37 Page - STMicroelectronics |
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37 / 129 page  DocID029656 Rev 2 37/129 ST25R3911B Functional overview 71 Figure 15. SPI communication: direct command Direct command chaining As shown in Figure 16, direct commands with immediate execution can be followed by another SPI mode (Read, Write or FIFO) without deactivating the /SS signal in between. Figure 16. SPI communication: direct command chaining SPI timing Table 7. SPI timing Symbol Parameter Min Typ Max Unit Comments General timing (VDD = VDD_IO = VSP_D = 3.3 V, 25 °C) TSCLK SCLK period 167 - - ns TSCLK=TSCLKL+TSCLKH, use of shorter SCLK period may lead to incorrect FIFO operation. TSCLKL SCLK low 70 - 1 - TSCLKH SCLK high 70 - - - TSSH SPI reset (/SS high) 100 - - - TNCSL /SS falling to SCLK rising 25 - - First SCLK pulse TNCSH SCLK falling to /SS rising 300 - - Last SCLK pulse TDIS Data in set-up time 10 - - - TDIH Data in hold time 10 - - - |
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