PIC16F716 datasheet(53/126 Pages) MICROCHIP

53 / 126 page

 2003 Microchip Technology Inc.

Preliminary

DS41206A-page 51

PIC16F716

FIGURE 8-1:

A/D BLOCK DIAGRAM

8.1

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 8-2. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD). The

source impedance affects the offset voltage at the

analog input (due to pin leakage current). The

maximum

recommended

impedance

for

analog

sources is 10 k

Ω. After the analog input channel is

selected (changed) this acquisition must be done

before the conversion can be started.

To calculate the minimum acquisition time, TACQ, see

the

PICmicro®

Mid-Range

Reference

Manual,

(DS33023). This equation calculates the acquisition

time to within 1/2 LSb error. The 1/2 LSb error is the

maximum error allowed for the A/D to meet its specified

accuracy.

FIGURE 8-2:

ANALOG INPUT MODEL

(Input voltage)

VIN

VREF

(Reference

voltage)

VDD

PCFG2:PCFG0

CHS2:CHS0

000

010

110

or 111

001

011

101

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

011

010

001

000

A/D

Converter

100

Note:

When the conversion is started, the

holding capacitor is disconnected from the

input pin.

CPIN

ANx

5 pF

VDD

VT = 0.6V

I leakage

RIC

≤ 1k

Sampling

Switch

RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567 8 9 10 11

Ω)

VDD

= 51.2 pF

± 500 nA

Legend:

CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

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