PIC16F716 datasheet(9/126 Pages) MICROCHIP

9 / 126 page

 2003 Microchip Technology Inc.

Preliminary

DS41206A-page 7

PIC16F716

2.0

MEMORY ORGANIZATION

There are two memory blocks in the PIC16F716

PICmicro®

microcontroller

device.

Each

block

(program memory and data memory) has its own bus

so that concurrent access can occur.

Additional information on device memory may be found

in the PICmicro® Mid-Range Reference Manual,

(DS33023).

2.1

Program Memory Organization

The PIC16F716 has a 13-bit program counter capable

of addressing an 8K x 14 program memory space. The

PIC16F716 has 2K x 14 words of program memory.

Accessing a location above the physically implemented

address will cause a wrap-around.

The Reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK OF

PIC16F716

2.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers (GPR)

and the Special Function Registers (SFR). Bits RP1

and RP0 of the Status register are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function

Registers

are

General

Purpose

Registers,

implemented as static RAM. All implemented banks

contain Special Function Registers. The upper 16

bytes of GPR space and some “high use” Special

Function Registers in Bank 0 are mirrored in Bank 1 for

code reduction and quicker access.

PC<12:0>

0000h

0004h

0005h

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

RP1:RP0(1)

(status<6:5>)

Bank

2(2)

3(2)

Note 1:

Maintain Status bit 6 clear to ensure

upward compatibility with future products.

Not implemented

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