PC87306 datasheet(26/110 Pages) NSC

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20 Configuration Registers (Continued)

A15

A10

LPTBA

When bit 6 of PNP0 is 0 this register is read only and is

forced to EFh This register may be modified only when the

parallel port is disabled Bit 0 (holding A2) must be 0 when

EPP is enabled and bit 6 of PNP0 is 1

Undefined results occur if a parallel port register is located

at the same address as an enabled SIO register due to

LPTBA configuration

Note

To modify LPTA base address first disable the parallel port then set

bit 6 of PNP0 to 1 then update LPTBA and then enable the parallel

port

2522 Plug and Play Configuration 0 Register (PNP0

Index e 1Bh)

Upon reset the implemented bits are initialized to 0

Bits 0 – 3

Reserved

Bit 4

Parallel Ports’ interrupt selection control

0 Parallel Port’s interrupt ie IRQ5 or IRQ7 is

selected via bits 0 and 1 of FAR register and

bit 3 of PTR register ie the selection is de-

pendent on the base IO address selection

This is the backward-compatible mode with

previous SIOs

1 Parallel Port’s interrupt ie IRQ5 or IRQ7 is

selected via bit 5 of PNP0 register

The selection is independent of the base IO

address

Bit 5

Parallel Port interrupt mapping

The parallel

port’s interrupt is routed to the following ISA in-

terrupt

0 IRQ5

1 IRQ7

When bit 4 of PNP0 register is ‘‘0’’ this bit is ig-

nored ie it does not determine Parallel Port in-

terrupt mapping

Bit 6

Parallel Port’s LPTA base address selection con-

trol

This bit enables software configuration of LPTA

base address via LPTBA configuration register

LPTA base address is selected when FARbit1 e

0 and FARbit0 e 1

There is no change in selection of LPTB and

LPTC via bits 0 – 1 of FAR

This bit is initialized to 0 during reset

0 LPTA is always 3BCh

This is the backward compatible mode with

previous SIOs

1 LPTA base address is selected via LPTBA

configuration register

Bit 7

Reserved

2523 Plug and Play Configuration 1 Register (PNP1

Index e 1Ch)

Upon reset the implemented bits are initialized to 0

Bit 0

UART1’s and UART2’s interrupt selection con-

trol

0 UART1’s interrupt ie

IRQ3 or IRQ4 is se-

lected via bits 2 and 3 of FAR register

UART2’s interrupt ie

IRQ3 or IRQ4 is se-

lected via bits 4 and 5 of FAR register

The selection is dependent on the base IO

address selection

This is the backward-compatible mode with

previous SIOs

1 UART1’s interrupt ie

IRQ3 or IRQ4 is se-

lected via bit 2 of PNP1 register

UART2’s interrupt ie

IRQ3 or IRQ4 is se-

lected via bit 6 of PNP1 register

The selection is independent of the base IO

address

Bit 1

Reserved

Bit 2

UART1 interrupt mapping UART1’s interrupt is

routed to the following ISA interrupt

0 IRQ3

1 IRQ4

When bit 0 of PNP1 register is 0 this bit is ig-

nored ie it does not determine UART1 interrupt

mapping

Bits 3 – 5

Reserved

Bit 6

UART2 interrupt mapping UART2’s interrupt is

routed to the following ISA interrupt

0 IRQ3

1 IRQ4

When bit 0 of PNP1 register is ‘‘0’’ this bit is ig-

nored ie it does not determine UART2 interrupt

mapping

Bit 7

Reserved

It is the software’s responsibility to route UART1’s and

UART2’s interrupts onto the ISA interrupts correctly

26 POWER-DOWN OPTIONS

There are two methods for entering the power-down mode

Both methods result in one of the two possible modes This

section associates the methods of entering power-down

with the resulting mode

Mode 1

The internal clock stops for a specific function (ie

UART1 andor UART2 andor FDC)

This mode is entered by any of the following actions

1 Clear the FER bit for the specific function that is powered

down See Section 251 FER bits 1 – 3

2 During reset set certain CFG 0 – 4 pins See Table 2-1

3 Execute the FDC Mode Command with PTR bit 1 e 0

(XTALCLK) See Section 426 LOW PWR

4 Set Data Rate Select Register bit 6 in the FDC high

with PTR bit 1 e 0 See Section 36 bit 6

Mode 2

The internal clocks are stopped for all enabled

functions

Note

Clocks to disabled functions are always inactive

This mode is entered by any of the following actions

1 Clear all FER bits for any enabled function See Section

251 FER bits 1 – 3

2 Clear PTR bits 1 (XTALCLK) and 2 (CSOUTPWDN se-

lect) Then assert the PWDN signal low See Section

253 PTR bits 12 and Section 10 PWDN pin

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