PC87306 datasheet(38/110 Pages) NSC

38 / 110 page

40 FDC Command Set Description (Continued)

Command Phase

TMR

IAF

IPS

LOW PWR

ETR

FWR

FRD

BST

R255

DENSEL

BFR

WLD

Head Settle

Execution Phase

Internal registers are written

Result Phase

None

TMR

Motor Timer mode Default after a software reset

0 e Timers for motor on and motor off are defined

for Mode 1 (See Specify command)

1 e

Timers for motor on and motor off are defined

for Mode 2 (See Specify command)

IAF

Index Address Format Default after a software reset

0 e The controller formats tracks with the Index Ad-

dress Field included (IBM and Perpendicular for-

mat)

1 e

The controller formats tracks without including

the Index Address Field (ISO format)

IPS

Implied Seek Default after a software reset

0 e The implied seek bit in the command byte of a

read write scan or verify is ignored Implied

seeks could still be enabled by the EIS bit in the

Configure command

1 e

The IPS bit in the command byte of a read write

scan or verify is enabled so that if it is set the

controller performs seek and sense interrupt op-

erations before executing the command

LOW

PWR

Low Power mode Default after a software reset

00 e Completely disable the low power mode

01 e

Automatic low power For 500 kbps operation

go into low power mode 512 ms after the head

unload timer times out For 250 kbps operation

the timeout period is doubled to 1s

10 e

Manual low power Go into low power mode

now

11 e

Not used

ETR

Extended Track Range Default after a software re-

set

0 e Track number is stored as a standard 8-bit value

compatible with the IBM ISO and Perpendicular

formats This allows access of up to 256 tracks

during a seek operation

1 e

Track number is stored as a 12-bit value The

upper four bits of the track value are stored in

the upper four bits of the head number in the

sector Address Field This allows access of up to

4096 tracks during a seek operation With this bit

set an extra byte is required in the Seek Com-

mand Phase and Sense Interrupt Result Phase

FWR

FIFO Write Disable for mP write transfers to control-

ler Default after a software reset if LOCK is 0 If

LOCK is 1 FWR retains its value after a software

reset

Note

This bit is only valid if the FIFO is enabled in the Configure

command If the FIFO is not enabled in the Configure com-

mand then this bit is a don’t care

0 e Enable FIFO mP write transfers druing the Exe-

cution Phase use the internal FIFO

1 e

Disable FIFO All write data transfers take place

without the FIFO

FRD

FIFO Read Disable for mP read transfers from con-

troller Default after a software reset if LOCK is 0 If

LOCK is 1 FRD retains its value after a software re-

set

Note

This bit is only valid if the FIFO is enabled in the Configure

command If the FIFO is not enabled in the Configure com-

mand then this bit is a don’t care

0 e Enable FIFO mP read transfers during the Exe-

cution Phase use the internal FIFO

1 e

Disable FIFO All read data transfers take place

without the FIFO

BST

Burst Mode Disable Default after a software reset if

LOCK is 0 If LOCK is 1 BST retains its value after a

software reset

Note

This bit is only valid if the FIFO is enabled in the Configure

command If the FIFO is not enabled in the Configure com-

mand then this bit is a don’t care

0 e Burst mode enabled for FIFO Execution Phase

data transfers

1 e

Non-Burst mode enabled The DRQ or IRQ6 pin

is strobed once for each byte to be transferred

while the FIFO is enabled

R255

Recalibrate Step Pulses The bit determines the

maximum number of recalibrate step pulses the con-

troller issues before terminating with an error De-

fault after a software reset

0 e Maximum of 85 recalibrate step pulses If ETR

1 controller issues 3925 recalibrate step

pulses maximum

1 e

Maximum of 255 recalibrate step pulses If ETR

1 controller issues 4095 maximum recali-

brate step pulses

DENSEL

Density Select Pin Configuration This 2-bit value

configures the Density Select output to one of

three possible modes The default mode config-

ures the DENSEL pin according to the state of bit

6 of ASC after a data rate has been selected

That is if ASC6 is high the DENSEL pin is active

high for the 500 kbps and 1 Mbps data rates If

ASC6 is low the DENSEL pin is active low for the

500 kbps and 1 Mbps data rates See Table 4-3

In addition to these modes the DENSEL output

can be set to always low or always high as

shown in Table 4-4 This allows the user more

flexibility with new drive types

TABLE 4-3 DENSEL Default Encoding

Data Rate

DENSEL Pin Definition

ASC6 e 1

ASC6 e 0

250 kbps

Low

High

300 kbps

Low

High

500 kbps

High

Low

1 Mbps

High

Low

When TUP bit 1 e 0 a Data Rate of 1 Mbps is selected

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