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PC87306 Datasheet(PDF) 37 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87306
Description  PC87306 SuperI/OTM Enhanced Sidewinder Lite Floppy Disk Controller, Keyboard Controller, Real-Time Clock, Dual UARTs, Infrared Interface, IEEE 1284 Pa
PDF  110 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87306 Datasheet(HTML) 37 Page - National Semiconductor (TI)

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40 FDC Command Set Description (Continued)
Notes
TLC12379 – 29
A1 e Data Pattern of A1 Clock Pattern of 0A
C2 e Data Pattern of C2 Clock Pattern of 14
All byte counts in decimal
All byte values in hex
CRC uses standard polynomial x16 a x12 a x5 a 1
Perpendicular Format GAP2 e 41 bytes for 1 Mbps and 2 Mbps
All other data rates use GAP2 e 22 bytes
FIGURE 4-2 IBM Perpendicular and ISO Formats Supported by the Format Command
414 Invalid Command
If an invalid command (illegal Opcode byte in the Command
Phase) is received by the controller the controller responds
with ST0 in the Result Phase The controller does not gen-
erate an interrupt during this condition Bits 6 and 7 in the
MSR are both set to a 1 indicating to the mP that the con-
troller is in the Result Phase and the contents of ST0 must
be read The system reads an 80h value from ST0 indicating
an invalid command was received
Command Phase
Invalid Op Codes
Execution Phase
None
Result Phase
Status Register 0 (80h)
415 Lock Command
The Lock command allows the user full control of the FIFO
parameters after a software reset If the LOCK bit is set to 1
then the FIFO THRESH and PRETRK bits in the Configure
command are not affected by a software reset In addition
the FWR FRD and BST bits in the Mode command are
unaffected by a software reset If the LOCK is 0 (default
after a hardware reset) then the above bits are set to their
default values after a software reset This command is use-
ful if the system designer wishes to keep the FIFO enabled
and retain the other FIFO parameter values (such as
THRESH) after a software reset
After the command byte is written the result byte must be
read before continuing to the next command The execution
of the Lock command is not performed until the result byte
is read by the mP If the part is reset after the command byte
is written but before the result byte is read then the Lock
command execution is not performed This is done to pre-
vent accidental execution of the Lock command
Command Phase
LOCK0010100
Execution Phase
Internal Lock register is written
Result Phase
000LOCK0000
416 Mode Command
This command is used to select the special features of the
controller The bits for the Command Phase bytes are
shown in Section 41 Command Set Summary and their
function is described below These bits are set to their de-
fault values after a hardware reset The default value of
each bit is denoted by a ‘‘bullet’’ to the left of each item The
value of each parameter after a software reset is explained
37



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