PC87306 datasheet(62/110 Pages) NSC

62 / 110 page

50 FDC Functional Description (Continued)

57 DATA RATE SELECTION

The data rate can be chosen two different ways with the

FDC For PC compatible software the Configuration Control

for the floppy controller The lower bits D1 and D0 are used

in the CCR to set the data rate The other bits should be set

to zero See Table 3-7 for the data rate select encoding

The data rate can also be set using the Data Rate Select

ter are used to set the data rate The encoding of these bits

is exactly the same as those in the CCR The remainder of

the bits in the DSR are used for other functions Consult the

The data rate is determined by the last value that is written

to either the CCR or the DSR In other words either the

CCR or the DSR can override the data rate selection of the

other register When the data rate is selected the micro-

engine and data separator clocks are scaled appropriately

Also the DRATE0 and DRATE1 output pins will reflect the

state of the data select bits that were last written to either

the CCR or the DSR

58 WRITE PRECOMPENSATION

Write precompensation is a way of preconditioning the

WDATA output signal to adjust for the effects of bit shift on

the data as it is written to the disk surface Bit shift is caused

by the magnetic interaction of data bits as they are written

to the disk surface and has the effect of shifting these data

bits away from their nominal position in the serial MFM or

FM data pattern Data that is subject to bit shift is much

harder to read by a data separator and can cause soft read

errors Write precompensation predicts where bit shift could

occur within a data pattern It then shifts the individual data

bits early late or not at all such that when they are written

to the disk the resultant shifted data bits will be back in their

nominal position

The FDC supports software programmable write precom-

pensation Upon power up the default write precomp values

will be used (see Table 3-6) The programmer can choose a

different value of write precomp with the DSR register if

desired (see Table 3-5) Also on power up the default start-

ing track number for write precomp is track zero This start-

ing track number for write precomp can be changed with the

Configure command

59 FDC LOW POWER MODE LOGIC

The FDC section of the PC87306 supports two low power

modes described here in detail Other low power modes of

the PC87306 are described in Section 25 Details concern-

ing entering and exiting low power mode via setting Date

Rate Select Register bit 6 or by executing the FDC Mode

Command are covered below and in Section 316 and Sec-

tion 416 The microcode is driven from the clock so it will

be disabled while the clock is off The FDC clock is always

disabled upon entering this mode however the oscillator is

only disabled when PTR1 e 1 Upon entering the power-

down state the RQM (Request For Master) bit in the MSR

will be cleared

There are two modes of low power in the floppy controller

manual low power and automatic low power Manual low

power is enabled by writinga1tobit6ofthe DSR The chip

will go into low power immediately This bit will be cleared to

0 after the chip is brought out of low power Manual low

power can also be accessed via the Mode command The

function of the manual low power mode is a logical OR func-

tion between the DSR low power bit and the Mode com-

mand manual low power bit setting

Automatic low power mode will switch the controller into low

power 500 ms (at the 500 kbps MFM data rate) after it has

entered the idle state Once the auto low power mode is set

it does not have to be set again and the controller will auto-

matically go into low power mode after it has entered the

idle state Automatic low power mode can only be set with

the Mode command

There are two ways the FDC section can recover from the

power-down state 1) The part will power up after a software

reset via the DOR or DSR Since a software reset requires

reinitialization of the controller this method can be undesir-

able 2) The part will also power up after a read or write to

either the Data Register or Main Status Register This is the

preferred method of power up since all internal register val-

ues are retained It may take a few milliseconds for the os-

cillator to stabilize and the mP will be prevented from issu-

ing commands during this time through the normal Main

Status Register protocol That is the RQM bit in the MSR

will be a 0 until the oscillator has stabilized When the con-

troller has completely stabilized from power up the RQM bit

in the MSR is set to 1 and the controller can continue where

it left off

The Data Rate Select Digital Output and Configuration

Control Registers are unaffected by the power-down mode

They will remain active It is up to the user to ensure that the

Motor and Drive Select signals are turned off

Note

If the power to an external oscillator driving the PC87306 is to be

independently removed during the FDC low power mode it must not

be done until 2 ms after the FDC low power command is issued

510 RESET OPERATION

The floppy controller can be reset by hardware or software

Hardware reset is enacted by pulsing the Master Reset in-

put pin A hardware reset will set all of the user addressable

registers and internal registers to their default values The

Specify command values will be don’t cares so they must

be reinitialized The major default conditions are FIFO dis-

abled FIFO threshold e 0 Implied Seeks disabled and

Drive Polling enabled

A software reset can be performed through the Digital Out-

put Register or Data Rate Select Register The DSR reset

bit is self-clearing while the DOR reset bit is not self-clear-

ing If the LOCK bit in the Lock command was set to a 1

previous to the software reset the FIFO THRESH and

PRETRK parameters in the Configure command will be re-

tained In addition the FWR FRD and BST parameters in

the Mode command will be retained if LOCK is set to 1 This

function eliminates the need for total reinitialization of the

controller after a software reset

After a hardware (assuming the FDC is enabled in the FER)

or software reset the Main Status Register is immediately

available for read access by the mP It will return a 00h value

until all the internal registers have been updated and the

data separator is stabilized When the controller is ready to

receive a command byte the MSR will return a value of 80h

(Request for Master bit is set) The MSR is guaranteed to

return the 80h value within 25 ms after a hardware or soft-

ware reset All other user addressable registers other than

the Main Status Register and Data Register (FIFO) can be

accessed at any time even while the part is in reset

PC87306 Datasheet(PDF) 62 Page - National Semiconductor (TI)

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