TNETV2665FIBZDUA6 datasheet(50/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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Table 2-18. Host-Port Interface Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

Host-Port Interface (HPI)

HD0/VLYNQ_SCRUN/

IPU

AD18/GP[58]

DVDD33

HD1/VLYNQ_RXD0/

AD16/GP[59]

HD2/VLYNQ_RXD1/

AD17/GP[60]

HD3/VLYNQ_RXD2/

PCBE2/GP[61]

HD4/VLYNQ_RXD3/

PFRAME/GP[62]

HD5/VLYNQ_TXD0/

PIRDY/GP[63]

HD6/VLYNQ_TXD1/

PTRDY/GP[64]

This pin is multiplexed between HPI, VLYNQ or EMAC (MII),

HD7/VLYNQ_TXD2/

PCI, and GPIO.

PDEVSEL/GP[65]

I/O/Z

In HPI mode, these pins are host-port data pins HD[15:0]

HD8/VLYNQ_TXD3/

IPD

(I/O/Z) and are multiplexed internally with the HPI address

PPERR/GP[66]

DVDD33

lines.

HD9/MCOL/

PSTOP/GP[67]

HD10/MCRS/

PSERR/GP[68]

HD11/MTXD3/

PCBE1/GP[69]

HD12/MTXD2/

PPAR/GP[70]

HD13/MTXD1/

AD14/GP[71]

HD14/MTXD0/

AD15/GP[72]

HD15/MTXCLK/

AD12/GP[73]

This pin is multiplexed between HPI, EMAC (MII), PCI, and

HHWIL/MRXDV/

IPD

GPIO.

I/O/Z

AD13/GP[74]

DVDD33

In HPI mode, this pin is half-word identification input HHWIL

(I).

This pin is multiplexed between HPI, EMAC (MII), PCI, and

GPIO.

HCNTL1/MTXEN/

IPD

In HPI mode, this pin is control input 1 HCNTL1 (I). The state

I/O/Z

AD11/GP[75]

DVDD33

of HCNTL1 and HCNTL0 determines if address, data, or

control information is being transmitted between an external

host and the C6424.

This pin is multiplexed between HPI, EMAC (MII), PCI, and

GPIO.

HCNTL0/MRXER/

IPD

In HPI mode, this pin is control input 0 HCNTL0 (I). The state

I/O/Z

AD10/GP[76]

DVDD33

of HCNTL1 and HCNTL0 determines if address, data, or

control information is being transmitted between an external

host and the C6424.

This pin is multiplexed between HPI, EMAC (MII), PCI, and

HR/W/MRXCLK/

IPD

I/O/Z

GPIO.

AD8/GP[77]

DVDD33

In HPI mode, this pin is host read or write select HR/W(I).

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 3.9.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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