TNETV2665FIBZDUA6 datasheet(74/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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As shown in Table 3-4 and Table 3-5, at device reset the Boot Controller defaults the DSPBOOTADDR to

one of two values based on the boot mode selected. In all boot modes, the C64x+ is immediately released

from reset and begins executing from address location indicated in DSPBOOTADDR.

•

Internal Bootloader ROM (0x0010 0000): For most boot modes, the DSPBOOTADDR defaults to the

internal Bootloader ROM so that the DSP can immediately execute the bootloader code in the internal

ROM. The bootloader code decodes the captured BOOTMODE, FASTBOOT, PCIEN, and PLLMS

information (in the BOOTCFG register) to determine the proper boot operation.

Note: For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code

disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the bootloader code, all C64x+

memories are configured as all RAM. If cache use is required, the application code must explicitly

enable the cache. For more information on boot modes, see Section 3.4.1, Boot Modes. For more

information on the bootloader, see the Using the TMS320C642x Bootloader Application Report

(literature number SPRAAK5).

•

EMIFA Chip Select Space 2 (0x4200 0000): The EMIFA ROM Direct Boot in PLL Bypass Mode

(BOOTCFG settings BOOTMODE[3:0] = 0100b, FASTBOOT = 0) is the only exception where the

DSPBOOTADDR defaults to the EMIFA Chip Select Space 2. The DSP begins execution directly from

the external ROM at this EMIFA space.

For more information how the bootloader code handles each boot mode, see the Using the TMS320C642x

Bootloader Application Report (literature number SPRAAK5).

3.4.1.1

FASTBOOT

When C6424 exits pin reset (RESET or POR released), the PLL Controllers (PLLC1 and PLLC2) default

to PLL Bypass Mode. This means the PLLs are disabled, and the MXI/CLKIN clock input is driving the

chip. All the clock domain divider ratios discussed in Section 6.3.4, C6424 Power and Clock Domains, still

apply. For example, assume an MXI/CLKIN frequency of 25 MHz—meaning the internal clock source for

EMIFA is at CLKDIV3 domain = 25 MHz/3 = 8.3 MHz, a very slow clock. In addition, the EMIFA registers

are reset to the slowest configuration which translates to very slow peripheral operation/boot.

To optimize boot time, the user should reprogram clock settings via the PLLC as early as possible during

the boot process. The FASTBOOT pin facilitates this operation by allowing the device to boot at a faster

clock rate.

Except for the EMIFA ROM Direct Boot in PLL Bypass Mode (BOOTCFG settings BOOTMODE[3:0] =

0100b, FASTBOOT = 0), all other boot modes default to executing from the Internal Bootloader ROM. The

first action that the bootloader code takes is to decode the boot mode. If the FASTBOOT option is

selected (BOOTCFG.FASTBOOT = 1), the bootloader software begins by programming the PLLC1

(System PLLC) to PLL Mode to give the device a slightly faster operation before fetching code from

external devices. The exact PLL multiplier that the bootloader uses is determined by the PLLMS[2:0]

settings, as shown in Table 3-5 and Table 3-6.

Some boot modes must be accompanied with FASTBOOT = 1 so that the corresponding peripheral can

run at a reasonable rate to communicate to the external device(s). This includes PCI boot.

Note: PLLC2 still stays in PLL Bypass Mode, the bootloader does not reconfigure it.

3.4.1.2

Selecting FASTBOOT PLL Multiplier

Table 3-5 and Table 3-6 show the PLL multipliers used by the bootloader code during fastboot

(FASTBOOT = 1) and the resulting device frequency. The user is responsible for selecting the bootmode

with the appropriate PLL multiplier for their MXI/CLKIN clock source so that the device speed and PLL

frequency range requirements are met. For the PLLC1 Clock Frequency Ranges, see Table 6-15, PLLC1

Clock Frequency Ranges in Section 6.7.1, PLL1 and PLL2.

The following are guidelines for PLL output frequency and device speed (frequency):

Device Configurations

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