LNBH24L

LNBH24 software description

Doc ID 16857 Rev 2

17/25

X = don’t care

Note:

Values are typical unless otherwise specified.

7.5

Power-ON I²C interface reset

The I²C interface built in the LNBH24L is automatically reset at power-on. As long as the

respond to any I²C command and the system registers (SR) are initialized to all zeroes, thus

becomes operative and the SRs can be configured by the main microprocessor. This is due

to 500 mV of hysteresis provided in the UVL threshold to avoid false re-triggering of the

Power-ON reset circuit.

7.6

Address pins

For each section of the LNBH24L it is possible to select two I²C interface addresses by

means of the relevant ADDR pin. The ADDR pins are TTL compatible and can be set as per

hereafter address pins characteristics see Table 11.

7.7

DiSEqC™ implementation for each section A/B

LNBH24L helps system designer to implement DiSEqC 1.x protocol by allowing an easy

the system to the specification is thus not implied by the bare use of the LNBH24L (see

DiSEqC 1.x operation descriptions and typical application circuits).

Table 8.

Register

TEST1

TEST2

TEST3

LLC

VSEL

EN

OTF

OLF

Function

These bits are read

exactly the same as

they were left after

last write operation

XX

X

These bits status must be disregarded by the

MCU.