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DS2148 Datasheet(PDF) 9 Page - Dallas Semiconductor |
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DS2148 Datasheet(HTML) 9 Page - Dallas Semiconductor |
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9 / 75 page  DS2148/Q48 9 of 75 TRANSMIT LOGIC Figure 3-3 4. PIN DESCRIPTION The DS2148 can be controlled in a parallel port mode, a serial port mode, or a hardware mode (Table 4-1, 4-2, and 4-3). The parallel and serial port modes are described in Section 3, and the hardware mode is described below. BUS INTERFACE SELECTION Table 4-1 BIS1 BIS0 PBTS BUS INTERFACE TYPE 0 0 0 Muxed Intel 0 0 1 Muxed Motorola 0 1 0 Nonmuxed Intel 0 1 1 Nonmuxed Motorola 1 0 - Serial Port 1 1 - Hardware BPV Insert mux B8ZS/ HDB3 Coder Logic Error Insert mux OR Gate OR Gate CCR3.1 CCR1.6 CCR2.2 CCR3.0 CCR3.4 CCR3.3 TPOS TNEG To Remote Loopback PRBS Generator Loop Code Generator Clock Invert Loss Of Transmit Clock Detect TCLK CCR2.1 RCLK JACLK (derived from MCLK) CCR1.0 CCR1.1 CCR1.2 1 0 mux mux OR Gate To LOTC Output Pin 0 1 0 1 AND Gate Routed to All Blocks tx bd SR.5 |
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