R5F11BBC datasheet(45/143 Pages) RENESAS

45 / 143 page

RL78/G1F

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)

R01DS0246EJ0110 Rev. 1.10

Page 45 of 140

Aug 12, 2016

Note 1.

The value must also be equal to or less than fMCK/4.

Note 2.

Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.

Caution

Select the normal input buffer and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin

products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SDAr pin and the normal output mode for

the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh).

(Remarks are listed on the next page.)

(5)

During communication at same potential (simplified I2C mode)

(TA = -40 to +85°C, 1.6 V

≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V)

(2/2)

Parameter

Symbol

Conditions

HS (high-speed main)

mode

LS (low-speed main)

mode

LV (low-voltage main)

mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Data setup time

(reception)

tSU: DAT

2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

1/fMCK + 85 Note 2

1/fMCK + 145 Note 2

1.8 V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1/fMCK + 145 Note 2

1.8 V

≤ EVDD0 < 2.7 V,

Cb = 100 pF, Rb = 5 k

1/fMCK + 230 Note 2

1.7 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

1/fMCK + 290 Note 2

1.6 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

—

1/fMCK + 290 Note 2

Data hold time

(transmission)

tHD: DAT 2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

305

1.8 V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

355

1.8 V

≤ EVDD0 < 2.7 V,

Cb = 100 pF, Rb = 5 k

405

1.7 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

405

1.6 V

≤ EVDD0 < 1.8 V,

Cb = 100 pF, Rb = 5 k

—

405

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