R5F564MFDDFB datasheet(147/228 Pages) RENESAS

147 / 228 page

R01DS0173EJ0110 Rev.1.10

Page 147 of 228

Oct 24, 2016

RX64M Group

5. Electrical Characteristics

5.3.1

Reset Timing

Figure 5.1

Reset Input Timing at Power-On

Figure 5.2

Reset Input Timing

Table 5.10

Reset Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

RES# pulse

width

Power-on

tRESWP

—

Figure 5.1

Deep software standby mode

tRESWD

0.6

—

Figure 5.2

Software standby mode, low-speed operating

mode 2

tRESWS

0.3

—

Programming or erasure of the code flash

memory, or programming, erasure or blank

checking of the data flash memory

tRESWF

200

—

μs

Other than above

tRESW

200

—

μs

Waiting time after release from the RES# pin reset

tRESWT

—

tLcyc

Figure 5.1

Internal reset time

(independent watchdog timer reset, watchdog timer reset,

software reset)

tRESW2

108

—

116

tLcyc

VCC

RES#

Internal reset signal

(Low is valid)

tRESWP

tRESWT

RES#

Internal reset signal

(Low is valid)

tRESWD, tRESWS, tRESWF, tRESW

tRESWT

R5F564MFDDFB Datasheet(PDF) 147 Page - Renesas Technology Corp

R5F564MFDDFB Datasheet(HTML) 147 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL