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RT3607CE Datasheet(PDF) 38 Page - Richtek Technology Corporation |
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RT3607CE Datasheet(HTML) 38 Page - Richtek Technology Corporation |
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38 / 69 page  38 RT3607CE www.richtek.com DS3607CE-01 June 2016 © Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 19. DVID Compensation Table 6 show the DVID_Threshold on the SET1 pin with internal 80 μA current source and Table 7 describes DVID_Width settings in SET2 pin with external voltage divider. For example, 39.67mV DVID_Threshold (SR = 11.25mV/ μs) / 119mV DVID_threshold (SR = 33.75mV/ μs) and 36μs DVID_Width are designed (OCP sets as 110% ICCMAX, RSET sets as 133% low frequency ramp / 200% high frequency ramp). According to the Table 6 and Table 7, the DVID_Threshold set voltage should be between 0.4254V to 0.4473V and the DVID_Width set voltage should be between 1.051V to 1.073V. Please note that a high accuracy resistor is needed for this setting, <1% error tolerance is recommended. VIN Gate Driver Q1 Q2 L RESR CO2 CPU C2 Charge current Induced charge current signal CO1 Ai R1 R2 C1 + - EA + - COMP CCRCOT tON VID Transition IDROOP VID Output voltage VIN VID Virtual Charge Current Slew Rate Control Virtual Charge Current Generator + DVID Event SET1 |
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