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RT3607CE Datasheet(PDF) 43 Page - Richtek Technology Corporation

Part # RT3607CE
Description  Multi-Phase PWM Controller for CPU Core Power Supply
PDF  69 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT3607CE Datasheet(HTML) 43 Page - Richtek Technology Corporation

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43
RT3607CE
DS3607CE-01 June 2016
www.richtek.com
©
Copyright 2016 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
Ramp Compensation
The G-NAVPTM topology is one type of ripple based control
that has fast transient response and can lower BOM cost.
However, ripple based control usually has poor noise
immunity. The RT3607CE provides the ramp compensation
to increase noise immunity and reduce jitter at the
switching node. Figure 20 shows the ramp compensation.
Figure 20. Ramp Compensation
Noise Margin
VCOMP
Noise Margin
IMON-VREF
w/o ramp compensation
w/ ramp compensation
IMON-VREF
VCOMP
For the RT3607CE, the ramp compensation also needs
to be considered during mode transition from PS0/1 to
PS2. For achieving smooth mode transition into PS2, a
proper ramp compensation design is necessary. Since
the ramp compensation needs to be proportional to the
on-time, the RAMP is set as
S
F
133%
.
400k
Quick Response (QR) Mechanism
When the transient load step-up becomes quite large, it
is difficult for loop response to meet the energy transfer.
Hence, that output voltage generate undershoot to fail
specification. The RT3607CE has Quick Response (QR)
mechanism being able to improve this issue. It adopts a
nonlinear control mechanism which can disable
interleaving function and simultaneously turn on all UGATE
one pulse at instantaneous step-up transient load to restrain
the output voltage drooping. Figure 21 shows the QR
behavior.
Figure 21. Quick Response Mechanism
The output voltage signal behavior needs to be detected
so that QR mechanism can be trigged. The output voltage
signal is via a remote sense line to connect at the VSEN
pin which is shown in Figure 22. The QR mechanism needs
to set QR width and QR threshold. Both definitions are
shown in Figure 21. A proper QR mechanism set can meet
different applications. The SET2 can set QR threshold and
QR width by internal current source 80
μA with multi-
function pin setting mechanism.
Figure 22. Simplified QR Trigger Schematic
For example, QR threshold 20mV/10mV at PS0/PS1 and
2.22 x TON QR width are set. According to Table 8, the
set voltage should be between 0.4504V and 0.4723V.
Please note that a high accuracy resistor is needed for
this setting accuracy, <1% error tolerance is
recommended. In Table 8, there are some “NA” marks
in QRWIDTH section. It means that users should not use
it to avoid the possibility of shift digital code due to
tolerance concern.
QR Threshold
QR Width
PWM1
PWM2
PWM3
PWM4
VCORE
Load
VSEN
QR Pulse
Generation
Circuit
CMP
+
-
QR_width
QR_TH



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