NŸ

+

PD

+

±

Ÿ

+

+

Ÿ

+

V3 2.5 V

Ÿ

V4 2.5 V

50

Ÿ input

matching

Gain of -10 V/V

Copyright © 2017, Texas Instruments Incorporated

29

OPA838

www.ti.com

SBOS867 – AUGUST 2017

Product Folder Links: OPA838

Submit Documentation Feedback

Copyright © 2017, Texas Instruments Incorporated

Figure 75. Inverting With Input Impedance Matching

Table 2. Inverting Recommended Resistor Values

AVERAGE

(OHMS)

ACTUAL (V/V)

GAIN (dB)

–6

1180

196

67.1

66.5

49.7

–6.02

15.59

–7

1370

196

67.1

66.5

49.7

–6.99

16.89

–8

1540

191

67.7

68.1

50.2

–8.06

18.13

–9

1690

187

68.2

68.1

49.9

–9.04

19.12

–10

1870

187

68.2

68.1

49.9

–10

20

–11

2050

187

68.2

68.1

49.9

–10.96

20.80

–12

2210

182

68.9

68.1

49.6

–12.14

21.69

–13

2370

182

68.9

68.1

49.6

–13.02

22.29

–14

2550

182

68.9

68.1

49.6

–14.01

22.93

–15

2740

182

68.9

68.1

49.6

–15.05

23.55

–16

2870

178

69.5

69.8

50.1

–16.12

24.15

–17

3090

182

68.9

69.8

50.5

–16.98

24.6

–18

3240

178

69.5

69.8

50.1

–18.20

25.2

–19

3400

178

69.5

69.8

50.1

–19.10

25.62

–20

3570

178

69.5

69.8

50.1

–20.06

26.04

9.1.3 Output DC Error Calculations

The OPA838 can provide excellent DC signal accuracy due to high open-loop gain, high common-mode

rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full

advantage of this low input offset voltage, pay careful attention to input bias current cancellation. The low-noise

input stage for the OPA838 has a relatively high input bias current (1.6 µA typical out the pins) but with a close

match between the two input currents. This is a negative rail input device using PNP input devices where the

base current flows out of the device pins. A large resistor to ground on the V+ input shifts positively because of

the input bias current. The mismatch between the two input bias currents is very low, typically only ±20 nA of

input offset current. Match the DC source impedances out of the two inputs to reduce the total output offset

voltage. For example, one way to add bias current cancellation to the circuit in Figure 68 is to insert a 165-Ω