OPA838IDBVT datasheet(31/41 Pages) TI1

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Vindiff

OPA838

R1 500

R2 500

VCM

RF 3.57

NŸ

RF 3.57

NŸ

RG1 88.7

CCM

10nF

VCC

Vodiff

High Gain

Differential

I/O

VEE

BI F

I R

4kTR

OPA838

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Dividing this expression by the noise gain (NG = 1 + RF / RG) gives the equivalent input referred spot noise

voltage at the noninverting input, as shown in Equation 4.

(4)

Using the resistor values shown in Table 1 with RS = 0 Ω results in a constant input referred voltage noise of

2.86nV /

√Hz. Reducing the resistor values brings this number closer to the intrinsic 1.9 nV / √Hz of the OPA838.

Adding RS for bias current cancellation in noninverting mode adds the noise from RS to the total output noise, as

shown in Equation 3. In inverting mode, the RS bias current cancellation resistor must be bypassed with a

capacitor for the best noise performance.

9.1.5 High-Gain Differential I/O Designs

A high-gain differential-to-differential I/O circuit can be used to drive a second-stage FDA or a differential-to-

single-ended stage. This circuit is frequently used in applications where high input impedance is required (for

example, if the source cannot be loaded). Figure 76 shows an example design where the differential gain is 41

V/V. An added element between the two RG resistors increases the noise gain for the common-mode feedback. It

is important to provision for the added element because a decompensated VFA (like the OPA838) often

oscillates without it in this circuit. With only the RG elements in the differential I/O design, the common-mode

feedback is unity-gain and often causes high-frequency, common-mode oscillations. To resolve this issue, split

the RG elements in half and add a low-impedance path such as a capacitor or a DC reference between the two

RG values.

Figure 77. High-Gain Differential I/O Stage

Integrated solutions are available, but the OPA838 device provides a low-power, high-frequency solution. For

best CMRR performance, resistors must be matched. A good rule is CMRR

≈ the resistor tolerance; so 0.1%

tolerance provides approximately 60-dB CMRR.

9.1.5.1 Differential I/O Design Requirements

As an example design, start with the circuit in Figure 77.

•

Set the target gain and split the RG element in half. For this example, target a gain of 41 V/V.

•

Assess the DC common-mode biasing on the noninverting inputs. The DC biasing must be in range and have

a gain of 1 to the output. This is not shown in Figure 76

•

If a DC reference is used as the mid-R G bias, setting the reference equal to the noninverting input bias

voltage sets the output common-mode to that voltage. Using a capacitor as shown in Figure 76 accomplishes

the same results.

9.1.5.2 Detailed Design Procedure

•

Set the total R G value near the high gain values using Table 1. This 178-Ω total must be split for a center tap

to increase the common-mode noise gain, as shown by the 88.7-Ω value in Figure 77.

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