OPA838IDBVT datasheet(34/41 Pages) TI1

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Frequency (MHz)

100

103

0.001

0.01

0.1

D075

Gain output pin

Gain Load (dB)

GBP

0.707

2 R C

¦ PD[

3dB

GBP

2 C

3dB

GBP

2 R C

OPA838

SBOS867 – AUGUST 2017

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sampling glitch and speed settling time.

9.1.7.1 Detailed Design Procedure

The primary design requirement is to set the achievable transimpedance gain and compensate the operational

amplifier with CF for the desired response shape. A detailed transimpedance design methodology is available in

Transimpedance Considerations for High-Speed Amplifiers. With a source capacitance set and the amplifier

selected to provide a particular gain bandwidth product, the achievable transimpedance gain and resulting

Butterworth bandwidth are tightly coupled as Equation 5 shows. Use Equation 6 to solve for a maximum RF

value. When the RF is selected, the feedback pole is set by Equation 7 to be at .707 of the characteristic

frequency. At that compensation point, the closed-loop bandwidth is that characteristic frequency with a

Butterworth response.

•

With the 100-pF source capacitance, 300-MHz gain bandwidth product, and the 2.2-MHz closed-loop

bandwidth target in the transimpedance stage, solve Equation 6 for a maximum gain of 100 kΩ.

•

Set the feedback pole at 0.707 times that 2.2-MHz Butterworth bandwidth. This sets the target 1 / (2π × R F ×

CF) = 1.55 MHz. Solving for CF sets the target to 1 pF

•

If DC precision is desired, add a 100-kΩ resistor to ground on the noninverting input. If DC precision is not

required, ground the noninverting input

•

Add a resistor noise filtering capacitor in parallel with the 100-kΩ resistor.

•

Add a small series resistor isolating this capacitor from the noninverting input.

•

Select a final filter capacitor for the load. (In this example, a value of 2.2 nF is used as a typical SAR input

capacitor.)

•

Add a series resistor to the final filter capacitor to form a 1-MHz pole. In this example, that is 73.2 Ω.

•

Confirm this resistor is greater than the minimum recommended value shown in Figure 49.

(5)

(6)

(7)

Implementing this design and simulating the performance using the TINA model for the response to the output

pin and to the final capacitive load shows the expected results of Figure 81. Here the exact 2.2-MHz flat

Butterworth response to the output pin is shown with the final single pole rolloff at 1 MHz at the final 2.2-nF

capacitor.

Figure 81. Small Signal Response for 100-kΩ Transimpedance Gain

OPA838IDBVT Datasheet(PDF) 34 Page - Texas Instruments

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