MPC7450EC datasheet(34/52 Pages) MOTOROLA

34 / 52 page

MPC7450 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Package Description

1.8

Package Description

The following sections provide the package parameters and mechanical dimensions for the CBGA package.

1.8.1

Package Parameters for the MPC7450, 483 CBGA

The package parameters are as provided in the following list. The package type is 29

× 29 mm, 483-lead

ceramic ball grid array (CBGA).

Package outline

× 29 mm

Interconnects

483 (22

× 22 ball array – 1)

Pitch

1.27 mm (50 mil)

Minimum module height

—

Maximum module height

3.22 mm

Ball diameter

0.89 mm (35 mil)

VDD

J9, J11, J13, J15, K10, K12, K14, L9, L11,

L13, L15, M10, M12, M14, N9, N11, N13,

N15, P10, P12, P14

—

N/A

Notes:

OVDD supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls

(L3CTL[0:1]); GVDD supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7],

L3_ECHO_CLK[0:3], and L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and VDD supplies power to the

processor core and the PLL (after ﬁltering to become AVDD). For actual recommended value of Vin or supply

voltages, see Table 4.

These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.

To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET

(selects 2.5 V). To program the L3 interface, connect L3VSEL to either GND (selects 1.8 V) or to HRESET

(selects 2.5 V) or to HRESET (selects 1.5 V). If used, pulldown resistors should be less than 250

Ω.

Ignored in 60x bus mode.

This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at

HRESET going high.

This signal must be negated during reset, by pull-up to OVDD or negation by ¬HRESET (inverse of HRESET), to

ensure proper operation.

Internal pull-up on die.

These pins require weak pull-up resistors (for example, 4.7 k

Ω) to maintain the control signals in the negated

state after they have been actively negated and released by the MPC7450 and other bus masters.

These input signals for factory use only and must be pulled down to GND for normal machine operation.

10. This pin can externally enable the performance monitor counters (PMC) if they are internally enabled by the

software. If it will not be used to control the PMC, it should be pulled down to GND so that the software can

enable the PMC.

11. Unused address pins must be pulled down to GND.

12. This test signal is recommended to be tied to HRESET; however, other conﬁgurations will not adversely affect

performance.

13. These signals must be pulled down to GND if unused or if the MPC7450 is in 60x bus mode.

14. This signal must be asserted during reset, by pull-down to GND or assertion by HRESET, to ensure proper

operation.

15. Power must be supplied to GVDD, even when the L3 interface is disabled or unused.

Table 15. Pinout Listing for the MPC7450, 483 CBGA Package (continued)

Signal Name

Pin Number

Active

I/O

I/F Select1

Notes

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

MPC7450EC Datasheet(PDF) 34 Page - Motorola, Inc

MPC7450EC Datasheet(HTML) 34 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL