MPC7450EC datasheet(8/52 Pages) MOTOROLA

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MPC7450 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Comparison with the MPC7400

Out-of-Order Window Size in Execution Queues

SFX Integer Units

1 Entry

× 3 Queues

1 Entry

× 2 Queues

Vector Units

In Order, 4 Queues

In Order, 2 Queues

Scalar Floating-Point Unit

In Order

Branch Processing Resources

Prediction Structures

BTIC, BHT, Link Stack

BTIC, BHT

BTIC Size, Associativity

128-Entry, 4-Way

64-Entry, 4-Way

BHT Size

2K-Entry

512-Entry

Link Stack Depth

None

Unresolved Branches Supported

Branch Taken Penalty (BTIC Hit)

Minimum Misprediction Penalty

Execution Unit Timings (Latency-Throughput)

Aligned Load (Integer, Float, Vector)

3-1, 4-1, 3-1

2-1, 2-1, 2-1

Misaligned Load (Integer, Float, Vector)

4-2, 5-2, 4-2

3-2, 3-2, 3-2

L1 Miss, L2 Hit Latency

6 (9)

9 (11)1

SFX (aDd Sub, Shift, Rot, Cmp, Logicals)

1-1

Integer Multiply (32

× 8, 32 × 16, 32 × 32)

3-1, 3-1, 4-2

2-1, 3-2, 5-4

Scalar Float

5-1

3-1

VSFX (Vector Simple)

1-1

VCFX (Vector Complex)

4-1

3-1

VFPU (Vector Float)

4-1

VPER (Vector Permute)

2-1

1-1

MMUs

MMUs (Instruction and Data)

128-Entry, 2-Way

Tablewalk Mechanism

Hardware + Software

Hardware

L1 I Cache/D Cache Features

Size

32K/32K

Associativity

8-Way

Locking Granularity/Style

4-Kbyte/Way

Full Cache

Parity on I Cache

Word

None

Parity on D Cache

Byte

None

Number of D Cache Misses (Load/Store)

5/1

8 (Any Combination)

Data Stream Touch Engines

4 Streams

On-Chip Cache Features

Cache Level

None (Except L1)

Table 1. Microarchitecture Comparison (continued)

Microarchitectural Specs

MPC7450

MPC7400/MPC7410

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

MPC7450EC Datasheet(PDF) 8 Page - Motorola, Inc

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